diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-03-10 00:02:11 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-03-10 00:02:11 +0000 |
| commit | ebe8678619fe7bca2fd4f65830192a7559af46c3 (patch) | |
| tree | a16f01389a0d8b50c40d7377d40b11255923ebf3 /nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h | |
| parent | 7960235bf41496b7d26d2362c9889c56c1e6415b (diff) | |
| download | px4-nuttx-ebe8678619fe7bca2fd4f65830192a7559af46c3.tar.gz px4-nuttx-ebe8678619fe7bca2fd4f65830192a7559af46c3.tar.bz2 px4-nuttx-ebe8678619fe7bca2fd4f65830192a7559af46c3.zip | |
Add peripheral support for the STM32 F2 family
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4471 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h b/nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h index 642f4d9c7..ff1661313 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h @@ -52,7 +52,7 @@ #define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ #define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ -#ifdef CONFIG_STM32_STM32F40XX +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ #endif @@ -99,7 +99,7 @@ /* Debug MCU APB1 freeze register */ -#ifdef CONFIG_STM32_STM32F40XX +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ # define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ @@ -121,7 +121,7 @@ /* Debug MCU APB2 freeze register */ -#ifdef CONFIG_STM32_STM32F40XX +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ # define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ # define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ |