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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-04-03 14:26:05 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-04-03 14:26:05 +0000 |
| commit | 139456d3cb1a8c7be9e48d765eda23b15d8c8bad (patch) | |
| tree | beda77a9181d9e274d066c6c466423325b8d8f8a /nuttx/arch/arm/src/stm32/chip/stm32_i2c.h | |
| parent | f5d629b65b9588ddae1333f06aa392083c284949 (diff) | |
| download | px4-nuttx-139456d3cb1a8c7be9e48d765eda23b15d8c8bad.tar.gz px4-nuttx-139456d3cb1a8c7be9e48d765eda23b15d8c8bad.tar.bz2 px4-nuttx-139456d3cb1a8c7be9e48d765eda23b15d8c8bad.zip | |
New LIS331DL driver and VSN updates from Uros
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3457 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32_i2c.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_i2c.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_i2c.h b/nuttx/arch/arm/src/stm32/chip/stm32_i2c.h index 3510b2f41..00a24b355 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_i2c.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_i2c.h @@ -102,7 +102,7 @@ #define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */ #define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT) #define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN (1 << 9) /* Bit 9: Event Interrupt Enable */ +#define I2C_CR2_ITEVFEN (1 << 9) /* Bit 9: Event Interrupt Enable */ #define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */ #define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */ #define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */ @@ -135,6 +135,7 @@ #define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */ #define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */ #define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */ + /* Bit 5: Reserved */ #define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */ #define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */ #define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */ @@ -142,9 +143,12 @@ #define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */ #define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */ #define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */ + /* Bit 13: Reserved */ #define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */ #define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */ +#define I2C_SR1_ERRORMASK (I2C_SR1_BERR|I2C_SR1_ARLO|I2C_SR1_AF|I2C_SR1_OVR|I2C_SR1_PECERR) + /* Status register 2 */ #define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */ |