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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-05-20 15:51:37 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-05-20 15:51:37 -0600 |
| commit | 921386a847b6e610223d808f1ba718c6518ff403 (patch) | |
| tree | 07caa807a4e96c623e3048287ea4c6403195acd4 /nuttx/arch/arm/src/stm32/chip/stm32_pwr.h | |
| parent | 624f28e66b785245650c96e6ca2375cf37f505ff (diff) | |
| download | px4-nuttx-921386a847b6e610223d808f1ba718c6518ff403.tar.gz px4-nuttx-921386a847b6e610223d808f1ba718c6518ff403.tar.bz2 px4-nuttx-921386a847b6e610223d808f1ba718c6518ff403.zip | |
STM32L152: Better LOOPSPERMSEC; Need to set higher performance VOS
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32_pwr.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_pwr.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h index 9f1220ba9..430624d3b 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h @@ -108,9 +108,9 @@ # define PWR_CR_ULP (1 << 9) /* Ultralow power mode */ # define PWR_CR_FWU (1 << 10) /* Low power run mode */ # define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */ -# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) */ -# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) */ -# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) */ +# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */ +# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */ +# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) PLL VCO Max = 24MHz */ # define PWR_CR_LPRUN (1 << 14) /* Low power run mode */ #endif |