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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-21 17:11:17 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-21 17:11:17 +0000 |
| commit | ab83d9064ee2a16b518532d6f6da2ee89300beb4 (patch) | |
| tree | 707301139602b389e051d781265e7c0bdf927275 /nuttx/arch/arm/src/stm32/chip/stm32_pwr.h | |
| parent | c0a3967f7a05e6bef02a3277d4f4f0ffe2128514 (diff) | |
| download | px4-nuttx-ab83d9064ee2a16b518532d6f6da2ee89300beb4.tar.gz px4-nuttx-ab83d9064ee2a16b518532d6f6da2ee89300beb4.tar.bz2 px4-nuttx-ab83d9064ee2a16b518532d6f6da2ee89300beb4.zip | |
Add STM3240 pwr and rcc header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4110 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32_pwr.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_pwr.h | 36 |
1 files changed, 30 insertions, 6 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h index 8066845af..744fe03d9 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32/chip/stm32_pwr.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -37,6 +37,13 @@ #define __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H /************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +/************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -47,6 +54,8 @@ /* Register Addresses ***************************************************************/ +#define STM32_PWR_CR (STM32_PWR_BASE+STM32_PWR_CR_OFFSET) +#define STM32_PWR_CSR (STM32_PWR_BASE+STM32_PWR_CSR_OFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -69,11 +78,26 @@ # define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ #define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ +#ifdef CONFIG_STM32_STM32F40XX +# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ +# define PWR_CR_VOS (1 << 14) /* Bit 14: Regulator voltage scaling output selection */ +#endif + /* Power control/status register */ -#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ -#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ -#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ -#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ +#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ +#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ +#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ + +#ifdef CONFIG_STM32_STM32F40XX +# define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#endif + +#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ + +#ifdef CONFIG_STM32_STM32F40XX +# define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */ +# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ +#endif #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */ |