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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-04-15 16:42:09 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-04-15 16:42:09 +0000 |
| commit | 4c1ec63efccc4655f775e81504c8300007d2fae8 (patch) | |
| tree | d2cb3c532b4270402848bdae4348ff4ddfef856d /nuttx/arch/arm/src/stm32/chip/stm32_wdg.h | |
| parent | 7bf071be1a572106fab0f4508ab01312c934b94d (diff) | |
| download | px4-nuttx-4c1ec63efccc4655f775e81504c8300007d2fae8.tar.gz px4-nuttx-4c1ec63efccc4655f775e81504c8300007d2fae8.tar.bz2 px4-nuttx-4c1ec63efccc4655f775e81504c8300007d2fae8.zip | |
Implement STM32 IWDG driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4612 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32_wdg.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_wdg.h | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h b/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h index 495b017ed..64ef2e0ac 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32/chip/stm32_wdg.h * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -61,14 +61,14 @@ /* Register Addresses ***************************************************************/ -#define STM32_IWDG_KR (STM32_IWDG_OFFSET+STM32_IWDG_KR_OFFSET) -#define STM32_IWDG_PR (STM32_IWDG_OFFSET+STM32_IWDG_PR_OFFSET) -#define STM32_IWDG_RLR (STM32_IWDG_OFFSET+STM32_IWDG_RLR_OFFSET) -#define STM32_IWDG_SR (STM32_IWDG_OFFSET+STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) -#define STM32_WWDG_CR (STM32_WWDG_OFFSET+STM32_WWDG_CR_OFFSET) -#define STM32_WWDG_CFR (STM32_WWDG_OFFSET+STM32_WWDG_CFR_OFFSET) -#define STM32_WWDG_SR (STM32_WWDG_OFFSET+STM32_WWDG_SR_OFFSET) +#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -77,6 +77,11 @@ #define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ #define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) +#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ +#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ +#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ +#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ + /* Prescaler register (32-bit) */ #define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ @@ -94,6 +99,8 @@ #define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ #define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) +#define IWDG_RLR_MAX (0xfff) + /* Status register (32-bit) */ #define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ |