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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-05-28 18:10:41 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-05-28 18:10:41 +0000 |
| commit | f01a56f6ca729b143cb2a65c108fac534bc76f10 (patch) | |
| tree | 7528950e666f5c1c4597101dea6a21435bc00c86 /nuttx/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h | |
| parent | f92cfd55719458f036d7190e54f84b3a4658f2ca (diff) | |
| download | px4-nuttx-f01a56f6ca729b143cb2a65c108fac534bc76f10.tar.gz px4-nuttx-f01a56f6ca729b143cb2a65c108fac534bc76f10.tar.bz2 px4-nuttx-f01a56f6ca729b143cb2a65c108fac534bc76f10.zip | |
Update all STM32 F2 files so that they are the same as the corresponding F4 files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4778 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h index aa3c859e3..5de2a9b58 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * arch/arm/src/stm32/chip/stm32f20xxx_rcc.h * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -240,7 +240,7 @@ #define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ #define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ #define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 IO port I reset */ -#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA2 reset */ +#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */ #define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */ #define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */ #define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */ |