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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-05-18 15:32:50 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-05-18 15:32:50 -0600 |
| commit | 0941751a7c45cda72bd7c937ff873246a26f0551 (patch) | |
| tree | 56aeb50a9a20318ccbd205d728f1b1a41f51a0fe /nuttx/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h | |
| parent | 5e2568f8a24b9a25d7dbba3022fa742120dbc331 (diff) | |
| download | px4-nuttx-0941751a7c45cda72bd7c937ff873246a26f0551.tar.gz px4-nuttx-0941751a7c45cda72bd7c937ff873246a26f0551.tar.bz2 px4-nuttx-0941751a7c45cda72bd7c937ff873246a26f0551.zip | |
Add support for STM32L15X GPIOs
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h index f83e1224a..fef3f2149 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h @@ -56,7 +56,7 @@ #define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ #define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ #define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32_GPIO_ARFH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ #define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses ***************************************************************/ @@ -70,7 +70,7 @@ #define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) #define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) #define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOA_ARFH (STM32_GPIOA_BASE+STM32_GPIO_ARFH_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) #define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) @@ -82,7 +82,7 @@ #define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) #define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) #define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOB_ARFH (STM32_GPIOB_BASE+STM32_GPIO_ARFH_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) #define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) @@ -94,7 +94,7 @@ #define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) #define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) #define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOC_ARFH (STM32_GPIOC_BASE+STM32_GPIO_ARFH_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) #define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) @@ -106,7 +106,7 @@ #define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) #define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) #define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOD_ARFH (STM32_GPIOD_BASE+STM32_GPIO_ARFH_OFFSET) +#define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET) #define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) @@ -118,7 +118,7 @@ #define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) #define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) #define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOE_ARFH (STM32_GPIOE_BASE+STM32_GPIO_ARFH_OFFSET) +#define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET) #define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) @@ -130,7 +130,7 @@ #define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) #define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) #define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOF_ARFH (STM32_GPIOF_BASE+STM32_GPIO_ARFH_OFFSET) +#define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET) /* Register Bitfield Definitions ****************************************************/ |