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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-05-08 21:45:46 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-05-08 21:45:46 -0600 |
| commit | 4495dfb36135744a6f903e32ac2215b1f3ab0452 (patch) | |
| tree | 29dd68997222cae7922fa0e563e87bb0cf0b2071 /nuttx/arch/arm/src/stm32/chip | |
| parent | 1a90bb00a7075444cfd5ad2022a844d51752d192 (diff) | |
| download | px4-nuttx-4495dfb36135744a6f903e32ac2215b1f3ab0452.tar.gz px4-nuttx-4495dfb36135744a6f903e32ac2215b1f3ab0452.tar.bz2 px4-nuttx-4495dfb36135744a6f903e32ac2215b1f3ab0452.zip | |
Fix typo is STM32 ADC driver for F2 and F4: ADC not ACD
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f30xxx_adc.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_adc.h b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_adc.h index 40b493d5e..638acf748 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_adc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_adc.h @@ -243,22 +243,22 @@ /* ADC configuration register */ #define ADC_CFGR_DMACFG (1 << 1) /* Bit 0: Direct memory access configuration */ -#define ACD_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */ -#define ACD_CFGR_RES_MASK (3 << ACD_CFGR_RES_SHIFT) -# define ACD_CFGR_RES_12BIT (0 << ACD_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */ -# define ACD_CFGR_RES_10BIT (1 << ACD_CFGR_RES_SHIFT) /* 13 ADCCLK clyes */ -# define ACD_CFGR_RES_8BIT (2 << ACD_CFGR_RES_SHIFT) /* 11 ADCCLK clyes */ -# define ACD_CFGR_RES_6BIT (3 << ACD_CFGR_RES_SHIFT) /* 9 ADCCLK clyes */ +#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */ +#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT) +# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */ +# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 13 ADCCLK clyes */ +# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 11 ADCCLK clyes */ +# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 9 ADCCLK clyes */ #define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */ #define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ #define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT) # define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT) /* Event = 0..15 */ -#define ACD_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ -#define ACD_CFGR_EXTEN_MASK (3 << ACD_CFGR_EXTEN_SHIFT) -# define ACD_CFGR_EXTEN_NONE (0 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */ -# define ACD_CFGR_EXTEN_RISING (1 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */ -# define ACD_CFGR_EXTEN_FALLING (2 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */ -# define ACD_CFGR_EXTEN_BOTH (3 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */ +#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ +#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT) +# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */ +# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */ +# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */ +# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */ #define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ #define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ #define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ |