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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-22 17:43:11 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-22 17:43:11 +0000 |
| commit | 53f5ca28646b826fb344dd870540493b0e7f916b (patch) | |
| tree | ab1202821ed52d4677f84a1e79547df1befe2f87 /nuttx/arch/arm/src/stm32/chip | |
| parent | 84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a (diff) | |
| download | px4-nuttx-53f5ca28646b826fb344dd870540493b0e7f916b.tar.gz px4-nuttx-53f5ca28646b826fb344dd870540493b0e7f916b.tar.bz2 px4-nuttx-53f5ca28646b826fb344dd870540493b0e7f916b.zip | |
More changes, getting closer to a clean STM3240 compile
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4120 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h | 8 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h | 2 |
3 files changed, 11 insertions, 1 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h index bfd2857f2..3f97b3fd2 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h @@ -379,6 +379,14 @@ * sources/sinks of data. The requests from peripherals assigned to a stream * are simply OR'ed together before entering the DMA block. This means that only * one request on a given stream can be enabled at once. + * + * Alternative stream selections are provided with a numeric suffix like _1, _2, etc. + * The DMA driver, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * SPI3_RX connects via DMA STREAM0, then following should be application-specific + * mapping should be used: + * + * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 */ #define STM32_DMA_MAP(d,c,s) ((d) << 6 | (s) << 3 | (c)) diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h index dfa8ce5d5..c1704fdf2 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h @@ -320,7 +320,7 @@ /* GPIO port bit set/reset register */ #define GPIO_BSRR_SET(n) (1 << (n)) -#define GPIO_BSRR_RESET(n) (1 << ((n)+16) +#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) /* GPIO port configuration lock register */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h index 86a4436d5..5dd10ff6b 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h @@ -294,6 +294,7 @@ /* AHB1 Peripheral Clock enable register */ +#define RCC_AH1BENR_GPIOEN(n) (1 << (n)) #define RCC_AH1BENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */ #define RCC_AH1BENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */ #define RCC_AH1BENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */ @@ -371,6 +372,7 @@ /* RCC AHB1 low power modeperipheral clock enable register */ +#define RCC_AH1BLPENR_GPIOLPEN(n) (1 << (n)) #define RCC_AH1BLPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */ #define RCC_AH1BLPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */ #define RCC_AH1BLPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */ |