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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-04-12 21:52:04 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-04-12 21:52:04 +0000 |
commit | 85ef12a1dab5e00054441f7a174e794077363206 (patch) | |
tree | 1a677683547e6004a03c65e5a1c39d8e7212b3c2 /nuttx/arch/arm/src/stm32/chip | |
parent | 60f90714242cfb8c972b881425a21a6be33676b1 (diff) | |
download | px4-nuttx-85ef12a1dab5e00054441f7a174e794077363206.tar.gz px4-nuttx-85ef12a1dab5e00054441f7a174e794077363206.tar.bz2 px4-nuttx-85ef12a1dab5e00054441f7a174e794077363206.zip |
Kconfig update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4597 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip')
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h b/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h index ccf7f2982..bb2cfa809 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h @@ -166,10 +166,10 @@ #define STM32_OTGFS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ #define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 transfer size register */ -#define STM32_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 transfer size register */ -#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 transfer size register */ -#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 transfer size register */ +#define STM32_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ +#define STM32_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ +#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ +#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ #define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) #define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ @@ -894,7 +894,7 @@ #define OTGFS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ #define OTGFS_DIEPTSIZ_MCNT_MASK (3 << OTGFS_DIEPTSIZ_MCNT_SHIFT) /* Bit 31: Reserved, must be kept at reset value */ -/* Device OUT endpoint-0 transfer size register */ +/* Device OUT endpoint TxFIFO status register */ #define OTGFS_DTXFSTS_MASK (0xffff) |