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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-01-02 18:22:19 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-01-02 18:22:19 +0000 |
| commit | 227420dd5ecb981092e5db9340c6c7f081afbcf3 (patch) | |
| tree | 8e8f3e816f1c311702c10f0778a7bc06b880f437 /nuttx/arch/arm/src/stm32/stm32_adc.c | |
| parent | 5e8b86e69a7e259c60a97947702ceb441c07f709 (diff) | |
| download | px4-nuttx-227420dd5ecb981092e5db9340c6c7f081afbcf3.tar.gz px4-nuttx-227420dd5ecb981092e5db9340c6c7f081afbcf3.tar.bz2 px4-nuttx-227420dd5ecb981092e5db9340c6c7f081afbcf3.zip | |
Add support for STM32 Potentiometer via ADC3
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4252 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/stm32_adc.c')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_adc.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_adc.c b/nuttx/arch/arm/src/stm32/stm32_adc.c index 451bd3cd6..b0ecd1ab3 100644 --- a/nuttx/arch/arm/src/stm32/stm32_adc.c +++ b/nuttx/arch/arm/src/stm32/stm32_adc.c @@ -960,7 +960,6 @@ static void adc_reset(FAR struct adc_dev_s *dev) irqstate_t flags; uint32_t regval; int offset; - int ret; int i; avdbg("intf: ADC%d\n", priv->intf); @@ -1007,8 +1006,10 @@ static void adc_reset(FAR struct adc_dev_s *dev) regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); /* Set mode configuration (Independent mode) */ - + +#ifdef CONFIG_STM32_STM32F10XX regval |= ADC_CR1_IND; +#endif /* Initialize the Analog watchdog enable */ @@ -1017,10 +1018,19 @@ static void adc_reset(FAR struct adc_dev_s *dev) /* Enable interrupt flags */ regval |= ADC_CR1_ALLINTS; - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); - /* ADC1 CR2 Configuration */ + /* ADC CCR configuration */ + +#ifdef CONFIG_STM32_STM32F40XX + regval |= adc_getreg(priv, STM32_ADC_CCR_OFFSET); + regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK | + ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE); + regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2); + adc_putreg(priv, STM32_ADC_CCR_OFFSET, regval); +#endif + + /* ADC CR2 Configuration */ regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); @@ -1028,7 +1038,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) regval &= ~ADC_CR2_CONT; - /*Set ALIGN (Right = 0) */ + /* Set ALIGN (Right = 0) */ regval &= ~ADC_CR2_ALIGN; adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); @@ -1239,7 +1249,6 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; uint32_t adcsr; - uint32_t regval; int32_t value; /* Identifies the interruption AWD or EOC */ |