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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-01-10 16:25:52 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-01-10 16:25:52 +0000 |
| commit | 12d52c812dac2668031e68a783e13fd7f8b49510 (patch) | |
| tree | f09f02bab834f5f0a8ff1e582e32c942a87c827f /nuttx/arch/arm/src/stm32/stm32_dumpgpio.c | |
| parent | bfd6e961c47c3572c7c409c296b345966634c217 (diff) | |
| download | px4-nuttx-12d52c812dac2668031e68a783e13fd7f8b49510.tar.gz px4-nuttx-12d52c812dac2668031e68a783e13fd7f8b49510.tar.bz2 px4-nuttx-12d52c812dac2668031e68a783e13fd7f8b49510.zip | |
Correct GPIO dump output
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4288 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/stm32_dumpgpio.c')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_dumpgpio.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c index 71d3a3d74..b0ebc84d9 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c @@ -126,13 +126,17 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) { lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n", - getreg32(base + STM32_GPIO_CRH_OFFSET), getreg32(base + STM32_GPIO_CRL_OFFSET), - getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_CRH_OFFSET), + getreg32(base + STM32_GPIO_CRL_OFFSET), + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), getreg32(base + STM32_GPIO_LCKR_OFFSET)); lldbg(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n", getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR), - getreg32(STM32_AFIO_EXTICR1), getreg32(STM32_AFIO_EXTICR2), - getreg32(STM32_AFIO_EXTICR3), getreg32(STM32_AFIO_EXTICR4)); + getreg32(STM32_AFIO_EXTICR1), + getreg32(STM32_AFIO_EXTICR2), + getreg32(STM32_AFIO_EXTICR3), + getreg32(STM32_AFIO_EXTICR4)); } else { @@ -144,21 +148,26 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32_RCC_APB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) { - lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(STM32_GPIO_IDR_OFFSET), getreg32(STM32_GPIO_ODR_OFFSET), - getreg32(STM32_GPIO_BSRR_OFFSET), getreg32(STM32_GPIO_LCKR_OFFSET)); + lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); lldbg(" AFRH: %08x AFRL: %08x\n", - getreg32(STM32_GPIO_ARFH_OFFSET), getreg32(STM32_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_ARFH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { - lldbg(" GPIO%c not enabled: APB1ENR: %08x\n", - g_portchar[port], getreg32(STM32_RCC_APB1ENR)); + lldbg(" GPIO%c not enabled: AHB1ENR: %08x\n", + g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); } #else # error "Unsupported STM32 chip" |