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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-04-15 16:20:25 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-04-15 16:20:25 +0000 |
commit | 3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b (patch) | |
tree | 13d2c82c982b760b250741f7167faf0d509ecbc4 /nuttx/arch/arm/src/stm32/stm32_pwr.c | |
parent | f1893cbaf513c7f0fbca77240fc59707ad039734 (diff) | |
download | px4-nuttx-3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b.tar.gz px4-nuttx-3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b.tar.bz2 px4-nuttx-3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b.zip |
Add code changes from Uros
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3507 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/stm32_pwr.c')
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_pwr.c | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.c b/nuttx/arch/arm/src/stm32/stm32_pwr.c new file mode 100644 index 000000000..861d32b64 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.c @@ -0,0 +1,90 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_pwr.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise <uros.platise@isotel.eu> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/** \file + * \author Uros Platise + * \brief STM32 Power + * + * \addtogroup STM32_PWR + * \{ + */ + +#include <nuttx/config.h> +#include <nuttx/arch.h> + +#include <stdint.h> +#include <errno.h> + +#include "up_arch.h" +#include "stm32_pwr.h" + + +#if defined(CONFIG_STM32_PWR) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +static inline uint16_t stm32_pwr_getreg(uint8_t offset) +{ + return getreg32(STM32_PWR_BASE + offset); +} + + +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) +{ + putreg32(value, STM32_PWR_BASE + offset); +} + + +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) +{ + modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits); +} + + + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +void stm32_pwr_enablebkp(void) +{ + stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP); +} + + +#endif // defined(CONFIG_STM32_PWR) +/** \} */ |