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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-10-20 20:31:45 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-10-20 20:31:45 +0000 |
commit | a3e09fa8c08bcad385894a5284340ecbaaa72ea9 (patch) | |
tree | 008545f666c3fb4063b9af3a703d6165ebd710b6 /nuttx/arch/arm/src/stm32/stm32_rcc.c | |
parent | 9ad896685124fb84348254f9bafe4fa5f50d9f7b (diff) | |
download | px4-nuttx-a3e09fa8c08bcad385894a5284340ecbaaa72ea9.tar.gz px4-nuttx-a3e09fa8c08bcad385894a5284340ecbaaa72ea9.tar.bz2 px4-nuttx-a3e09fa8c08bcad385894a5284340ecbaaa72ea9.zip |
Add FSMC support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2163 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/stm32_rcc.c')
-rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_rcc.c | 44 |
1 files changed, 43 insertions, 1 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c index 10ed40912..972b036a4 100755 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c @@ -100,6 +100,47 @@ static inline void rcc_reset(void) putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ } +static inline void rcc_enableahb(void) +{ + uint32 regval; + + /* Always enable FLITF clock and SRAM clock */ + + regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN; + +#if CONFIG_STM32_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHBENR_DMA1EN; +#endif + +#if CONFIG_STM32_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHBENR_DMA2EN; +#endif + +#if CONFIG_STM32_CRC + /* CRC clock enable */ + + regval |= RCC_AHBENR_CRCEN; +#endif + +#if CONFIG_STM32_FSMC + /* FSMC clock enable */ + + regval |= RCC_AHBENR_FSMCEN; +#endif + +#if CONFIG_STM32_SDIO + /* SDIO clock enable */ + + regval |= RCC_AHBENR_SDIOEN; +#endif + + putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ +} + static inline void rcc_enableapb1(void) { uint32 regval; @@ -414,8 +455,9 @@ void stm32_clockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); } - /* Enable periperal clocking */ + /* Enable peripheral clocking */ + rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); } |