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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-09-28 19:14:37 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-09-28 19:14:37 +0000 |
commit | fa0e1e5d0b4bbbeb2af68e1517997dba6ef60ec9 (patch) | |
tree | 407649dda3a972888a1f1b3ddfb3592716cbf94a /nuttx/arch/arm/src/stm32/stm32_rcc.h | |
parent | a76921a3c964a7f32b973d9f676c92f84d63442f (diff) | |
download | px4-nuttx-fa0e1e5d0b4bbbeb2af68e1517997dba6ef60ec9.tar.gz px4-nuttx-fa0e1e5d0b4bbbeb2af68e1517997dba6ef60ec9.tar.bz2 px4-nuttx-fa0e1e5d0b4bbbeb2af68e1517997dba6ef60ec9.zip |
Add RCC support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2101 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/stm32_rcc.h')
-rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_rcc.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h index 21dd0efc5..a7227cd79 100755 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.h +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h @@ -63,16 +63,16 @@ /* Register Addresses ***************************************************************/ -#define STM32_RCC_CR (STM32_RCC_OFFSET+STM32_RCC_CR_OFFSET) -#define STM32_RCC_CFGR (STM32_RCC_OFFSET+STM32_RCC_CFGR_OFFSET) -#define STM32_RCC_CIR (STM32_RCC_OFFSET+STM32_RCC_CIR_OFFSET) -#define STM32_RCC_APB2RSTR (STM32_RCC_OFFSET+STM32_RCC_APB2RSTR_OFFSET) -#define STM32_RCC_APB1RSTR (STM32_RCC_OFFSET+STM32_RCC_APB1RSTR_OFFSET) -#define STM32_RCC_AHBENR (STM32_RCC_OFFSET+STM32_RCC_AHBENR_OFFSET) -#define STM32_RCC_APB2ENR (STM32_RCC_OFFSET+STM32_RCC_APB2ENR_OFFSET) -#define STM32_RCC_APB1ENR (STM32_RCC_OFFSET+STM32_RCC_APB1ENR_OFFSET) -#define STM32_RCC_BDCR (STM32_RCC_OFFSET+STM32_RCC_BDCR_OFFSET) -#define STM32_RCC_CSR (STM32_RCC_OFFSET+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) /* Register Bitfield Definitions ****************************************************/ |