Add code changes from Uros

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3507 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 26 insertions, 62 deletions

diff --git a/nuttx/arch/arm/src/stm32/stm32_rtc.h b/nuttx/arch/arm/src/stm32/stm32_rtc.h
index 4ebff07a9..467464664 100644
--- a/nuttx/arch/arm/src/stm32/stm32_rtc.h
+++ b/nuttx/arch/arm/src/stm32/stm32_rtc.h
@@ -1,8 +1,8 @@
 /************************************************************************************
  * arch/arm/src/stm32/stm32_rtc.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
+ *   Author: Uros Platise <uros.platise@isotel.eu>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -33,84 +33,48 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H
-#define __ARCH_ARM_SRC_STM32_STM32_RTC_H
-
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
+#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H
+#define __ARCH_ARM_SRC_STM32_STM32_RTC_H
+
 #include <nuttx/config.h>
 
 #include "chip.h"
+#include "chip/stm32_rtc.h"
+#include "chip/stm32_bkp.h"
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* Register Offsets *****************************************************************/
-
-#define STM32_RTC_CRH_OFFSET    0x0000    /* RTC control register High (16-bit) */
-#define STM32_RTC_CRL_OFFSET    0x0004    /* RTC control register low (16-bit) */
-#define STM32_RTC_PRLH_OFFSET   0x0008    /* RTC prescaler load register high (16-bit) */ 
-#define STM32_RTC_PRLL_OFFSET   0x000c    /* RTC prescaler load register low (16-bit) */
-#define STM32_RTC_DIVH_OFFSET   0x0010    /* RTC prescaler divider register high (16-bit) */
-#define STM32_RTC_DIVL_OFFSET   0x0014    /* RTC prescaler divider register low (16-bit) */
-#define STM32_RTC_CNTH_OFFSET   0x0018    /* RTC counter register high (16-bit) */
-#define STM32_RTC_CNTL_OFFSET   0x001c    /* RTC counter register low (16-bit) */
-#define STM32_RTC_ALRH_OFFSET   0x0020    /* RTC alarm register high (16-bit) */
-#define STM32_RTC_ALRL_OFFSET   0x0024    /* RTC alarm register low (16-bit) */
-
-/* Register Addresses ***************************************************************/
-
-#define STM32_RTC_CRH           (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET)
-#define STM32_RTC_CRL           (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET)
-#define STM32_RTC_PRLH          (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET)
-#define STM32_RTC_PRLL          (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET)
-#define STM32_RTC_DIVH          (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET)
-#define STM32_RTC_DIVL          (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET)
-#define STM32_RTC_CNTH          (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET)
-#define STM32_RTC_CNTL          (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET)
-#define STM32_RTC_ALRH          (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET)
-#define STM32_RTC_ALRL          (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET)
-
-/* Register Bitfield Definitions ****************************************************/
-
-/* RTC control register High (16-bit) */
+#define STM32_RTC_PRESCALER_SECOND      32767   /** Default prescaler to get a second base */
+#define STM32_RTC_PRESCALER_MIN         1       /** Maximum speed of 16384 Hz */
 
-#define RTC_CRH_SECIE           (1 << 0)  /* Bit 0 : Second Interrupt Enable*/
-#define RTC_CRH_ALRIE           (1 << 1)  /* Bit 1: Alarm Interrupt Enable*/
-#define RTC_CRH_OWIE            (1 << 2)  /* Bit 2: OverfloW Interrupt Enable*/
+#ifndef __ASSEMBLY__
 
-/* RTC control register low (16-bit) */
-
-#define RTC_CRL_SECF            (1 << 0)  /* Bit 0: Second Flag*/
-#define RTC_CRL_ALRF            (1 << 1)  /* Bit 1: Alarm Flag*/
-#define RTC_CRL_OWF             (1 << 2)  /* Bit 2: Overflow Flag*/
-#define RTC_CRL_RSF             (1 << 3)  /* Bit 3: Registers Synchronized Flag*/
-#define RTC_CRL_CNF             (1 << 4)  /* Bit 4: Configuration Flag*/
-#define RTC_CRL_RTOFF           (1 << 5)  /* Bit 5: RTC operation OFF*/
-
-/* RTC prescaler load register high (16-bit) */
-
-#define RTC_PRLH_PRL_SHIFT      (0)      /* Bits 3-0: RTC Prescaler Reload Value High */
-#define RTC_PRLH_PRL_MASK       (0x0f << RTC_PRLH_PRL_SHIFT)
-
-/* RTC prescaler divider register high (16-bit) */
-
-#define RTC_DIVH_RTC_DIV_SHIFT  (0)      /* Bits 3-0: RTC Clock Divider High */
-#define RTC_DIVH_RTC_DIV_MASK   (0x0f << RTC_DIVH_RTC_DIV_SHIFT)
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
 
 /************************************************************************************
- * Public Types
+ * Public Functions
  ************************************************************************************/
 
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+/** Set alarm output pin */
+EXTERN void stm32_rtc_settalarmpin(bool activate);
 
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
 
+/** \} */
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
 #endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */