Add support for SRAM on board the STM3240G-EVAL board

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4430 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 67 insertions, 30 deletions

diff --git a/nuttx/arch/arm/src/stm32/stm32_start.c b/nuttx/arch/arm/src/stm32/stm32_start.c
index 5f4a4c9c9..3f2f45b6b 100644
--- a/nuttx/arch/arm/src/stm32/stm32_start.c
+++ b/nuttx/arch/arm/src/stm32/stm32_start.c
@@ -75,49 +75,86 @@
  * Name: stm32_fpuconfig
  *
  * Description:
- *   Configure the FPU.
+ *   Configure the FPU.  Relative bit settings:
  *
- *   1. The MCU has an FPU, then enable full access to coprocessors CP10 and
- *      CP11.
+ *     CPACR:  Enables access to CP10 and CP11
+ *     CONTROL.FPCA: Determines whether the FP extension is active in the
+ *       current context:
+ *     FPCCR.ASPEN:  Enables automatic FP state preservation, then the
+ *       processor sets this bit to 1 on successful completion of any FP
+ *       instruction.
+ *     FPCCR.LSPEN:  Enables lazy context save of FP state. When this is
+ *       done, the processor reserves space on the stack for the FP state,
+ *       but does not save that state information to the stack.
  *
- *   if the common ARMv-7M interrupt vector handling is used (via
- *   CONFIG_ARMV7M_CMNVECTOR=y), then lazy floating point register saving is
- *   disabled and this function will also:
- *
- *   2. Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- *     with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
- *     are going to turn on CONTROL.FPCA for all contexts.
- *
- *   3. Set CONTROL.FPCA so that we always get the extended context frame
- *      with the volatile FP registers stacked above the basic context.
+ *  Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ *   - the CPACR permits access to CP10 and CP11, that give access to the FP
+ *     extension, or
+ *   - the CONTROL.FPCA bit is set to 1
  *
  ****************************************************************************/
 
 #ifdef CONFIG_ARCH_FPU
 #ifdef CONFIG_ARMV7M_CMNVECTOR
 
-#  define stm32_fpuconfig() \
-{ \
-  uint32_t regval;\
-  regval = getcontrol(); \
-  regval |= 1<<2; \
-  setcontrol(regval); \
-  regval = getreg32(NVIC_FPCCR); \
-  regval &= ~((1 << 31) | (1 << 30)); \
-  putreg32(regval, NVIC_FPCCR); \
-  regval = getreg32(NVIC_CPACR); \
-  regval |= ((3 << (2*10)) | (3 << (2*11))); \
-  putreg32(regval, NVIC_CPACR); \
+static inline void stm32_fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Set CONTROL.FPCA so that we always get the extended context frame
+   * with the volatile FP registers stacked above the basic context.
+   */
+
+  regval = getcontrol(); 
+  regval |= (1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
+   * are going to turn on CONTROL.FPCA for all contexts.
+   */
+
+  regval = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2*10)) | (3 << (2*11)));
+  putreg32(regval, NVIC_CPACR);
 }
 
 #else
 
-#  define stm32_fpuconfig() \
-{ \
-  uint32_t regval = getreg32(NVIC_CPACR); \
-  regval |= ((3 << (2*10)) | (3 << (2*11))); \
-  putreg32(regval, NVIC_CPACR); \
+static inline void stm32_fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Clear CONTROL.FPCA so that we do not get the extended context frame
+   * with the volatile FP registers stacked in the saved context.
+   */
+
+  regval = getcontrol(); 
+  regval &= ~(1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
+   * are going to keep CONTROL.FPCA off for all contexts.
+   */
+
+  regval = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2*10)) | (3 << (2*11)));
+  putreg32(regval, NVIC_CPACR);
 }
+
 #endif
 
 #else