diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-12-16 20:05:51 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-12-16 20:05:51 +0000 |
| commit | 891f61e86fcc0a4c42f25432016762b6aafb287e (patch) | |
| tree | f0447a687a6bc51494a5c24c81170ca3811b0c7f /nuttx/arch/arm/src/stm32 | |
| parent | c33cfd52449fc6c1b9211cb45618a77b544876e6 (diff) | |
| download | px4-nuttx-891f61e86fcc0a4c42f25432016762b6aafb287e.tar.gz px4-nuttx-891f61e86fcc0a4c42f25432016762b6aafb287e.tar.bz2 px4-nuttx-891f61e86fcc0a4c42f25432016762b6aafb287e.zip | |
Changing NuttX fixed size type names to C99 standard names -- things will be broken for awhile
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2359 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32')
33 files changed, 1058 insertions, 1046 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h index 9256521fb..f6430b2c1 100755 --- a/nuttx/arch/arm/src/stm32/chip.h +++ b/nuttx/arch/arm/src/stm32/chip.h @@ -41,10 +41,9 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Get customizations for each supported chip (only the STM32F103Z right now) */ diff --git a/nuttx/arch/arm/src/stm32/stm32_adc.h b/nuttx/arch/arm/src/stm32/stm32_adc.h index a9860bebc..b79b48c03 100755 --- a/nuttx/arch/arm/src/stm32/stm32_adc.h +++ b/nuttx/arch/arm/src/stm32/stm32_adc.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_bkp.h b/nuttx/arch/arm/src/stm32/stm32_bkp.h index 299ef48c8..fd69240e4 100644 --- a/nuttx/arch/arm/src/stm32/stm32_bkp.h +++ b/nuttx/arch/arm/src/stm32/stm32_bkp.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ #if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) diff --git a/nuttx/arch/arm/src/stm32/stm32_can.h b/nuttx/arch/arm/src/stm32/stm32_can.h index a35d8f996..9d8ca9454 100644 --- a/nuttx/arch/arm/src/stm32/stm32_can.h +++ b/nuttx/arch/arm/src/stm32/stm32_can.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* 3 TX mailboxes */ diff --git a/nuttx/arch/arm/src/stm32/stm32_dgbmcu.h b/nuttx/arch/arm/src/stm32/stm32_dgbmcu.h index 7757452f2..650b4b346 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dgbmcu.h +++ b/nuttx/arch/arm/src/stm32/stm32_dgbmcu.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Addresses ***************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_dma.c b/nuttx/arch/arm/src/stm32/stm32_dma.c index 4599baada..3050820d1 100755 --- a/nuttx/arch/arm/src/stm32/stm32_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32_dma.c @@ -38,8 +38,9 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> #include <semaphore.h> #include <debug.h> #include <errno.h> @@ -83,10 +84,10 @@ struct stm32_dma_s { - ubyte chan; /* DMA channel number (0-6) */ - ubyte irq; /* DMA channel IRQ number */ + uint8_t chan; /* DMA channel number (0-6) */ + uint8_t irq; /* DMA channel IRQ number */ sem_t sem; /* Used to wait for DMA channel to become available */ - uint32 base; /* DMA register channel base address */ + uint32_t base; /* DMA register channel base address */ dma_callback_t callback; /* Callback invoked when the DMA completes */ void *arg; /* Argument passed to callback function */ }; @@ -181,28 +182,28 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = /* Get non-channel register from DMA1 or DMA2 */ -static inline uint32 dmabase_getreg(struct stm32_dma_s *dmach, uint32 offset) +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(DMA_BASE(dmach->base) + offset); } /* Write to non-channel register in DMA1 or DMA2 */ -static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32 offset, uint32 value) +static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, DMA_BASE(dmach->base) + offset); } /* Get channel register from DMA1 or DMA2 */ -static inline uint32 dmachan_getreg(struct stm32_dma_s *dmach, uint32 offset) +static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(dmach->base + offset); } /* Write to channel register in DMA1 or DMA2 */ -static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32 offset, uint32 value) +static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, dmach->base + offset); } @@ -244,7 +245,7 @@ static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach) static void stm32_dmachandisable(struct stm32_dma_s *dmach) { - uint32 regval; + uint32_t regval; /* Disable all interrupts at the DMA controller */ @@ -272,7 +273,7 @@ static void stm32_dmachandisable(struct stm32_dma_s *dmach) static int stm32_dmainterrupt(int irq, void *context) { struct stm32_dma_s *dmach; - uint32 isr; + uint32_t isr; int chndx; /* Get the channel structure from the interrupt number */ @@ -447,10 +448,10 @@ void stm32_dmafree(DMA_HANDLE handle) * ****************************************************************************/ -void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr, size_t ntransfers, uint32 ccr) +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32 regval; + uint32_t regval; /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the @@ -498,11 +499,11 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr, size_t ntrans * ****************************************************************************/ -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, boolean half) +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; int irq; - uint32 ccr; + uint32_t ccr; DEBUGASSERT(handle != NULL); @@ -592,7 +593,7 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32 dmabase = DMA_BASE(dmach->base); + uint32_t dmabase = DMA_BASE(dmach->base); dmadbg("DMA Registers: %s\n", msg); dmadbg(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr); diff --git a/nuttx/arch/arm/src/stm32/stm32_exti.h b/nuttx/arch/arm/src/stm32/stm32_exti.h index c4e7947c1..b0e0329c2 100644 --- a/nuttx/arch/arm/src/stm32/stm32_exti.h +++ b/nuttx/arch/arm/src/stm32/stm32_exti.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ #ifdef CONFIG_STM32_CONNECTIVITYLINE diff --git a/nuttx/arch/arm/src/stm32/stm32_flash.h b/nuttx/arch/arm/src/stm32/stm32_flash.h index 8b22ae90b..414641aa1 100755 --- a/nuttx/arch/arm/src/stm32/stm32_flash.h +++ b/nuttx/arch/arm/src/stm32/stm32_flash.h @@ -41,12 +41,12 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" #include "stm32_memorymap.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_fsmc.h b/nuttx/arch/arm/src/stm32/stm32_fsmc.h index 86b8df8bd..ff0bba2ef 100644 --- a/nuttx/arch/arm/src/stm32/stm32_fsmc.h +++ b/nuttx/arch/arm/src/stm32/stm32_fsmc.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c index 10bf482cb..d10c9328b 100755 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.c +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c @@ -38,7 +38,9 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + +#include <stdint.h> +#include <stdbool.h> #include <debug.h> #include <arch/irq.h> @@ -59,7 +61,7 @@ * Private Data ****************************************************************************/ -static const uint32 g_gpiobase[STM32_NGPIO_PORTS] = +static const uint32_t g_gpiobase[STM32_NGPIO_PORTS] = { #if STM32_NGPIO_PORTS > 0 STM32_GPIOA_BASE, @@ -104,17 +106,17 @@ static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; * ****************************************************************************/ -int stm32_configgpio(uint32 cfgset) +int stm32_configgpio(uint32_t cfgset) { - uint32 base; - uint32 cr; - uint32 regval; - uint32 regaddr; + uint32_t base; + uint32_t cr; + uint32_t regval; + uint32_t regaddr; unsigned int port; unsigned int pin; unsigned int pos; unsigned int modecnf; - boolean input; + bool input; /* Verify that this hardware supports the select GPIO port */ @@ -215,7 +217,7 @@ int stm32_configgpio(uint32 cfgset) regval = getreg32(regaddr); shift = AFIO_EXTICR_EXTI_SHIFT(pin); regval &= ~(AFIO_EXTICR_PORT_MASK << shift); - regval |= (((uint32)port) << shift); + regval |= (((uint32_t)port) << shift); putreg32(regval, regaddr); } @@ -259,10 +261,10 @@ int stm32_configgpio(uint32 cfgset) * ****************************************************************************/ -void stm32_gpiowrite(uint32 pinset, boolean value) +void stm32_gpiowrite(uint32_t pinset, bool value) { - uint32 base; - uint32 offset; + uint32_t base; + uint32_t offset; unsigned int port; unsigned int pin; @@ -299,9 +301,9 @@ void stm32_gpiowrite(uint32 pinset, boolean value) * ****************************************************************************/ -boolean stm32_gpioread(uint32 pinset) +bool stm32_gpioread(uint32_t pinset) { - uint32 base; + uint32_t base; unsigned int port; unsigned int pin; @@ -329,10 +331,10 @@ boolean stm32_gpioread(uint32 pinset) ****************************************************************************/ #ifdef CONFIG_DEBUG -int stm32_dumpgpio(uint32 pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; - uint32 base; + uint32_t base; unsigned int port; unsigned int pin; diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h index c18d31557..43377fce5 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.h +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ #define STM32_NGPIO_PORTS ((STM32_NGPIO + 15) >> 4) diff --git a/nuttx/arch/arm/src/stm32/stm32_i2c.h b/nuttx/arch/arm/src/stm32/stm32_i2c.h index a37aaeeed..5df00d675 100755 --- a/nuttx/arch/arm/src/stm32/stm32_i2c.h +++ b/nuttx/arch/arm/src/stm32/stm32_i2c.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_internal.h b/nuttx/arch/arm/src/stm32/stm32_internal.h index bedec385c..d7e40ba63 100755 --- a/nuttx/arch/arm/src/stm32/stm32_internal.h +++ b/nuttx/arch/arm/src/stm32/stm32_internal.h @@ -41,7 +41,10 @@ ************************************************************************************/ #include <nuttx/config.h> + #include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> #include "up_internal.h" #include "chip.h" @@ -176,16 +179,16 @@ ************************************************************************************/ typedef FAR void *DMA_HANDLE; -typedef void (*dma_callback_t)(DMA_HANDLE handle, ubyte isr, void *arg); +typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t isr, void *arg); #ifdef CONFIG_DEBUG_DMA struct stm32_dmaregs_s { - uint32 isr; - uint32 ccr; - uint32 cndtr; - uint32 cpar; - uint32 cmar; + uint32_t isr; + uint32_t ccr; + uint32_t cndtr; + uint32_t cpar; + uint32_t cmar; }; #endif @@ -214,7 +217,7 @@ extern "C" { * and we will need to set the NVIC vector location to this alternative location. */ -extern uint32 stm32_vectors[]; /* See stm32_vectors.S */ +extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */ /************************************************************************************ * Public Function Prototypes @@ -248,7 +251,7 @@ EXTERN void stm32_clockconfig(void); * ************************************************************************************/ -EXTERN int stm32_configgpio(uint32 cfgset); +EXTERN int stm32_configgpio(uint32_t cfgset); /************************************************************************************ * Name: stm32_gpiowrite @@ -258,7 +261,7 @@ EXTERN int stm32_configgpio(uint32 cfgset); * ************************************************************************************/ -EXTERN void stm32_gpiowrite(uint32 pinset, boolean value); +EXTERN void stm32_gpiowrite(uint32_t pinset, bool value); /************************************************************************************ * Name: stm32_gpioread @@ -268,7 +271,7 @@ EXTERN void stm32_gpiowrite(uint32 pinset, boolean value); * ************************************************************************************/ -EXTERN boolean stm32_gpioread(uint32 pinset); +EXTERN bool stm32_gpioread(uint32_t pinset); /************************************************************************************ * Function: stm32_dumpgpio @@ -279,7 +282,7 @@ EXTERN boolean stm32_gpioread(uint32 pinset); ************************************************************************************/ #ifdef CONFIG_DEBUG -EXTERN int stm32_dumpgpio(uint32 pinset, const char *msg); +EXTERN int stm32_dumpgpio(uint32_t pinset, const char *msg); #else # define stm32_dumpgpio(p,m) #endif @@ -347,8 +350,8 @@ EXTERN void stm32_dmafree(DMA_HANDLE handle); * ****************************************************************************/ -EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr, - size_t ntransfers, uint32 ccr); +EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr); /**************************************************************************** * Name: stm32_dmastart @@ -363,7 +366,7 @@ EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr, ****************************************************************************/ EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, - void *arg, boolean half); + void *arg, bool half); /**************************************************************************** * Name: stm32_dmastop @@ -465,12 +468,12 @@ EXTERN int stm32_ethinitialize(int intf); struct spi_dev_s; enum spi_dev_e; -EXTERN void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, boolean selected); -EXTERN ubyte stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -EXTERN void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, boolean selected); -EXTERN ubyte stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -EXTERN void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, boolean selected); -EXTERN ubyte stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +EXTERN void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +EXTERN uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +EXTERN void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +EXTERN uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +EXTERN void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +EXTERN uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); /************************************************************************************ * Name: stm32_usbpullup @@ -485,7 +488,7 @@ EXTERN ubyte stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); ************************************************************************************/ struct usbdev_s; -EXTERN int stm32_usbpullup(FAR struct usbdev_s *dev, boolean enable); +EXTERN int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable); /************************************************************************************ * Name: stm32_usbsuspend @@ -499,7 +502,7 @@ EXTERN int stm32_usbpullup(FAR struct usbdev_s *dev, boolean enable); ************************************************************************************/ struct usbdev_s; -EXTERN void stm32_usbsuspend(FAR struct usbdev_s *dev, boolean resume); +EXTERN void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); /**************************************************************************** * Name: sdio_initialize @@ -528,7 +531,7 @@ EXTERN FAR struct sdio_dev_s *sdio_initialize(int slotno); * * Input Parameters: * dev - An instance of the SDIO driver device state structure. - * cardinslot - TRUE is a card has been detected in the slot; FALSE if a + * cardinslot - true is a card has been detected in the slot; false if a * card has been removed from the slot. Only transitions * (inserted->removed or removed->inserted should be reported) * @@ -537,7 +540,7 @@ EXTERN FAR struct sdio_dev_s *sdio_initialize(int slotno); * ****************************************************************************/ -EXTERN void sdio_mediachange(FAR struct sdio_dev_s *dev, boolean cardinslot); +EXTERN void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot); /**************************************************************************** * Name: sdio_wrprotect @@ -548,14 +551,14 @@ EXTERN void sdio_mediachange(FAR struct sdio_dev_s *dev, boolean cardinslot); * * Input Parameters: * dev - An instance of the SDIO driver device state structure. - * wrprotect - TRUE is a card is writeprotected. + * wrprotect - true is a card is writeprotected. * * Returned Values: * None * ****************************************************************************/ -EXTERN void sdio_wrprotect(FAR struct sdio_dev_s *dev, boolean wrprotect); +EXTERN void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect); #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 7ba448079..802679479 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -39,8 +39,8 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <stdint.h> #include <debug.h> #include <nuttx/irq.h> @@ -75,7 +75,7 @@ * Public Data ****************************************************************************/ -uint32 *current_regs; +uint32_t *current_regs; /**************************************************************************** * Private Data @@ -211,7 +211,7 @@ static int stm32_reserved(int irq, FAR void *context) * ****************************************************************************/ -static int stm32_irqinfo(int irq, uint32 *regaddr, uint32 *bit) +static int stm32_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) { DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); @@ -293,7 +293,7 @@ void up_irqinitialize(void) */ #ifdef CONFIG_STM32_DFU - putreg32((uint32)stm32_vectors, NVIC_VECTAB); + putreg32((uint32_t)stm32_vectors, NVIC_VECTAB); #endif /* Set all interrrupts (and exceptions) to the default priority */ @@ -378,9 +378,9 @@ void up_irqinitialize(void) void up_disable_irq(int irq) { - uint32 regaddr; - uint32 regval; - uint32 bit; + uint32_t regaddr; + uint32_t regval; + uint32_t bit; if (stm32_irqinfo(irq, ®addr, &bit) == 0) { @@ -403,9 +403,9 @@ void up_disable_irq(int irq) void up_enable_irq(int irq) { - uint32 regaddr; - uint32 regval; - uint32 bit; + uint32_t regaddr; + uint32_t regval; + uint32_t bit; if (stm32_irqinfo(irq, ®addr, &bit) == 0) { @@ -445,8 +445,8 @@ void up_maskack_irq(int irq) #ifdef CONFIG_ARCH_IRQPRIO int up_prioritize_irq(int irq, int priority) { - uint32 regaddr; - uint32 regval; + uint32_t regaddr; + uint32_t regval; int shift; DEBUGASSERT(irq >= STM32_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); diff --git a/nuttx/arch/arm/src/stm32/stm32_lowputc.c b/nuttx/arch/arm/src/stm32/stm32_lowputc.c index 2ba0f65a9..93e6b747f 100644 --- a/nuttx/arch/arm/src/stm32/stm32_lowputc.c +++ b/nuttx/arch/arm/src/stm32/stm32_lowputc.c @@ -38,8 +38,8 @@ **************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <stdint.h> #include <arch/board/board.h> #include "up_internal.h" @@ -224,7 +224,7 @@ void up_lowputc(char ch) /* Then send the character */ - putreg32((uint32)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET); #endif } @@ -241,9 +241,9 @@ void up_lowputc(char ch) void stm32_lowsetup(void) { #if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) - uint32 mapr; + uint32_t mapr; #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG) - uint32 cr; + uint32_t cr; #endif /* Enable the selected USARTs and configure GPIO pins need byed the diff --git a/nuttx/arch/arm/src/stm32/stm32_memorymap.h b/nuttx/arch/arm/src/stm32/stm32_memorymap.h index d07c91a2f..09b91185f 100755 --- a/nuttx/arch/arm/src/stm32/stm32_memorymap.h +++ b/nuttx/arch/arm/src/stm32/stm32_memorymap.h @@ -41,19 +41,19 @@ ************************************************************************************/
#include <nuttx/config.h>
-#include <sys/types.h>
+
#include "chip.h"
/************************************************************************************
- * Definitions
+ * Pre-processor Definitions
************************************************************************************/
/* FLASH and SRAM *******************************************************************/
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000 - Up to 512Kb */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 64Kb SRAM */
-#define STM32_SRAMBB_BASE 0x22000000 -#define STM32_PERIPH_BASE 0x40000000 +#define STM32_SRAMBB_BASE 0x22000000
+#define STM32_PERIPH_BASE 0x40000000
/* Register Base Address ************************************************************/
@@ -123,15 +123,15 @@ #define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: RC */
/* 0x40023400 - 0x40027fff: Reserved */
#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */
- /* 0x40030000 - 0x4fffffff: Reserved */ - -/* Peripheral BB base */ - -#define STM32_PERIPHBB_BASE 0x42000000 - -/* Flexible SRAM controller (FSMC) */ -
-#define STM32_FSMC_BASE 0xa0000000 + /* 0x40030000 - 0x4fffffff: Reserved */
+
+/* Peripheral BB base */
+
+#define STM32_PERIPHBB_BASE 0x42000000
+
+/* Flexible SRAM controller (FSMC) */
+
+#define STM32_FSMC_BASE 0xa0000000
/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
* address range
diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.h b/nuttx/arch/arm/src/stm32/stm32_pwr.h index 4b9964b09..bf2b733c3 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c index 543542309..22c67d120 100755 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c @@ -38,8 +38,8 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <stdint.h> #include <debug.h> #include <arch/board/board.h> @@ -69,7 +69,7 @@ static inline void rcc_reset(void) { - uint32 regval; + uint32_t regval; putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */ putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */ @@ -102,7 +102,7 @@ static inline void rcc_reset(void) static inline void rcc_enableahb(void) { - uint32 regval; + uint32_t regval; /* Always enable FLITF clock and SRAM clock */ @@ -143,7 +143,7 @@ static inline void rcc_enableahb(void) static inline void rcc_enableapb1(void) { - uint32 regval; + uint32_t regval; #if CONFIG_STM32_USB /* USB clock divider. This bit must be valid before enabling the USB @@ -286,7 +286,7 @@ static inline void rcc_enableapb1(void) static inline void rcc_enableapb2(void) { - uint32 regval; + uint32_t regval; /* Set the appropriate bits in the APB2ENR register to enabled the * selected APB2 peripherals. @@ -379,8 +379,8 @@ static inline void rcc_enableapb2(void) void stm32_clockconfig(void) { - uint32 regval; - volatile sint32 timeout; + uint32_t regval; + volatile int32_t timeout; /* Make sure that we are starting in the reset state */ diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h index eacb65522..c690033ee 100755 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.h +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_rtc.h b/nuttx/arch/arm/src/stm32/stm32_rtc.h index cd448277c..4ebff07a9 100644 --- a/nuttx/arch/arm/src/stm32/stm32_rtc.h +++ b/nuttx/arch/arm/src/stm32/stm32_rtc.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.c b/nuttx/arch/arm/src/stm32/stm32_sdio.c index b23da9a05..8500ae661 100644 --- a/nuttx/arch/arm/src/stm32/stm32_sdio.c +++ b/nuttx/arch/arm/src/stm32/stm32_sdio.c @@ -38,8 +38,9 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> #include <semaphore.h> #include <string.h> #include <assert.h> @@ -203,13 +204,13 @@ struct stm32_dev_s sem_t waitsem; /* Implements event waiting */ sdio_eventset_t waitevents; /* Set of events to be waited for */ - uint32 waitmask; /* Interrupt enables for event waiting */ + uint32_t waitmask; /* Interrupt enables for event waiting */ volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ WDOG_ID waitwdog; /* Watchdog that handles event timeouts */ /* Callback support */ - ubyte cdstatus; /* Card status */ + uint8_t cdstatus; /* Card status */ sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ worker_t callback; /* Registered callback function */ void *cbarg; /* Registered callback argument */ @@ -217,15 +218,15 @@ struct stm32_dev_s /* Interrupt mode data transfer support */ - uint32 *buffer; /* Address of current R/W buffer */ + uint32_t *buffer; /* Address of current R/W buffer */ size_t remaining; /* Number of bytes remaining in the transfer */ - uint32 xfrmask; /* Interrupt enables for data transfer */ + uint32_t xfrmask; /* Interrupt enables for data transfer */ /* DMA data transfer support */ - boolean widebus; /* Required for DMA support */ + bool widebus; /* Required for DMA support */ #ifdef CONFIG_SDIO_DMA - boolean dmamode; /* TRUE: DMA mode transfer */ + bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ #endif }; @@ -235,15 +236,15 @@ struct stm32_dev_s #ifdef CONFIG_SDIO_XFRDEBUG struct stm32_sdioregs_s { - ubyte power; - uint16 clkcr; - uint16 dctrl; - uint32 dtimer; - uint32 dlen; - uint32 dcount; - uint32 sta; - uint32 mask; - uint32 fifocnt; + uint8_t power; + uint16_t clkcr; + uint16_t dctrl; + uint32_t dtimer; + uint32_t dlen; + uint32_t dcount; + uint32_t sta; + uint32_t mask; + uint32_t fifocnt; }; struct stm32_sampleregs_s @@ -261,107 +262,107 @@ struct stm32_sampleregs_s /* Low-level helpers ********************************************************/ -static void stm32_takesem(struct stm32_dev_s *priv); -#define stm32_givesem(priv) (sem_post(&priv->waitsem)) -static inline void stm32_setclkcr(uint32 clkcr); -static void stm32_configwaitints(struct stm32_dev_s *priv, uint32 waitmask, - sdio_eventset_t waitevents, sdio_eventset_t wkupevents); -static void stm32_configxfrints(struct stm32_dev_s *priv, uint32 xfrmask); -static void stm32_setpwrctrl(uint32 pwrctrl); -static inline uint32 stm32_getpwrctrl(void); +static void stm32_takesem(struct stm32_dev_s *priv); +#define stm32_givesem(priv) (sem_post(&priv->waitsem)) +static inline void stm32_setclkcr(uint32_t clkcr); +static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, sdio_eventset_t wkupevents); +static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask); +static void stm32_setpwrctrl(uint32_t pwrctrl); +static inline uint32_t stm32_getpwrctrl(void); /* DMA Helpers **************************************************************/ #ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_sampleinit(void); -static void stm32_sdiosample(struct stm32_sdioregs_s *regs); -static void stm32_sample(struct stm32_dev_s *priv, int index); -static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg); -static void stm32_dumpsample(struct stm32_dev_s *priv, - struct stm32_sampleregs_s *regs, const char *msg); -static void stm32_dumpsamples(struct stm32_dev_s *priv); +static void stm32_sampleinit(void); +static void stm32_sdiosample(struct stm32_sdioregs_s *regs); +static void stm32_sample(struct stm32_dev_s *priv, int index); +static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg); +static void stm32_dumpsample(struct stm32_dev_s *priv, + struct stm32_sampleregs_s *regs, const char *msg); +static void stm32_dumpsamples(struct stm32_dev_s *priv); #else -# define stm32_sampleinit() -# define stm32_sample(priv,index) -# define stm32_dumpsamples(priv) +# define stm32_sampleinit() +# define stm32_sample(priv,index) +# define stm32_dumpsamples(priv) #endif #ifdef CONFIG_SDIO_DMA -static void stm32_dmacallback(DMA_HANDLE handle, ubyte isr, void *arg); +static void stm32_dmacallback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif /* Data Transfer Helpers ****************************************************/ -static ubyte stm32_log2(uint16 value); -static void stm32_dataconfig(uint32 timeout, uint32 dlen, uint32 dctrl); -static void stm32_datadisable(void); -static void stm32_sendfifo(struct stm32_dev_s *priv); -static void stm32_recvfifo(struct stm32_dev_s *priv); -static void stm32_eventtimeout(int argc, uint32 arg); -static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent); -static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupevent); +static uint8_t stm32_log2(uint16_t value); +static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl); +static void stm32_datadisable(void); +static void stm32_sendfifo(struct stm32_dev_s *priv); +static void stm32_recvfifo(struct stm32_dev_s *priv); +static void stm32_eventtimeout(int argc, uint32_t arg); +static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent); +static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupevent); /* Interrupt Handling *******************************************************/ -static int stm32_interrupt(int irq, void *context); +static int stm32_interrupt(int irq, void *context); /* SDIO interface methods ***************************************************/ /* Initialization/setup */ -static void stm32_reset(FAR struct sdio_dev_s *dev); -static ubyte stm32_status(FAR struct sdio_dev_s *dev); -static void stm32_widebus(FAR struct sdio_dev_s *dev, boolean enable); -static void stm32_clock(FAR struct sdio_dev_s *dev, +static void stm32_reset(FAR struct sdio_dev_s *dev); +static uint8_t stm32_status(FAR struct sdio_dev_s *dev); +static void stm32_widebus(FAR struct sdio_dev_s *dev, bool enable); +static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate); -static int stm32_attach(FAR struct sdio_dev_s *dev); +static int stm32_attach(FAR struct sdio_dev_s *dev); /* Command/Status/Data Transfer */ -static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32 cmd, - uint32 arg); -static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, - size_t nbytes); -static int stm32_sendsetup(FAR struct sdio_dev_s *dev, - FAR const ubyte *buffer, uint32 nbytes); -static int stm32_cancel(FAR struct sdio_dev_s *dev); - -static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32 cmd); -static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32 cmd, - uint32 *rshort); -static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32 cmd, - uint32 rlong[4]); -static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32 cmd, - uint32 *rshort); -static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32 cmd, - uint32 *rnotimpl); +static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg); +static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t nbytes); +static int stm32_sendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, uint32_t nbytes); +static int stm32_cancel(FAR struct sdio_dev_s *dev); + +static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); +static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]); +static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rnotimpl); /* EVENT handler */ -static void stm32_waitenable(FAR struct sdio_dev_s *dev, - sdio_eventset_t eventset); +static void stm32_waitenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); static sdio_eventset_t - stm32_eventwait(FAR struct sdio_dev_s *dev, uint32 timeout); -static void stm32_callbackenable(FAR struct sdio_dev_s *dev, - sdio_eventset_t eventset); -static int stm32_registercallback(FAR struct sdio_dev_s *dev, - worker_t callback, void *arg); + stm32_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout); +static void stm32_callbackenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static int stm32_registercallback(FAR struct sdio_dev_s *dev, + worker_t callback, void *arg); /* DMA */ #ifdef CONFIG_SDIO_DMA -static boolean stm32_dmasupported(FAR struct sdio_dev_s *dev); -static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, - FAR ubyte *buffer, size_t buflen); -static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, - FAR const ubyte *buffer, size_t buflen); +static bool stm32_dmasupported(FAR struct sdio_dev_s *dev); +static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, + FAR uint8_t *buffer, size_t buflen); +static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen); #endif /* Initialization/uninitialization/reset ************************************/ -static void stm32_callback(void *arg); -static void stm32_default(void); +static void stm32_callback(void *arg); +static void stm32_default(void); /**************************************************************************** * Private Data @@ -460,9 +461,9 @@ static void stm32_takesem(struct stm32_dev_s *priv) * ****************************************************************************/ -static inline void stm32_setclkcr(uint32 clkcr) +static inline void stm32_setclkcr(uint32_t clkcr) { - uint32 regval = getreg32(STM32_SDIO_CLKCR); + uint32_t regval = getreg32(STM32_SDIO_CLKCR); /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ @@ -495,7 +496,7 @@ static inline void stm32_setclkcr(uint32 clkcr) * ****************************************************************************/ -static void stm32_configwaitints(struct stm32_dev_s *priv, uint32 waitmask, +static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, sdio_eventset_t waitevents, sdio_eventset_t wkupevent) { @@ -528,7 +529,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32 waitmask, * ****************************************************************************/ -static void stm32_configxfrints(struct stm32_dev_s *priv, uint32 xfrmask) +static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) { irqstate_t flags; flags = irqsave(); @@ -552,9 +553,9 @@ static void stm32_configxfrints(struct stm32_dev_s *priv, uint32 xfrmask) * ****************************************************************************/ -static void stm32_setpwrctrl(uint32 pwrctrl) +static void stm32_setpwrctrl(uint32_t pwrctrl) { - uint32 regval; + uint32_t regval; regval = getreg32(STM32_SDIO_POWER); regval &= ~SDIO_POWER_PWRCTRL_MASK; @@ -578,7 +579,7 @@ static void stm32_setpwrctrl(uint32 pwrctrl) * ****************************************************************************/ -static inline uint32 stm32_getpwrctrl(void) +static inline uint32_t stm32_getpwrctrl(void) { return getreg32(STM32_SDIO_POWER) & SDIO_POWER_PWRCTRL_MASK; } @@ -613,9 +614,9 @@ static void stm32_sampleinit(void) #ifdef CONFIG_SDIO_XFRDEBUG static void stm32_sdiosample(struct stm32_sdioregs_s *regs) { - regs->power = (ubyte)getreg32(STM32_SDIO_POWER); - regs->clkcr = (uint16)getreg32(STM32_SDIO_CLKCR); - regs->dctrl = (uint16)getreg32(STM32_SDIO_DCTRL); + regs->power = (uint8_t)getreg32(STM32_SDIO_POWER); + regs->clkcr = (uint16_t)getreg32(STM32_SDIO_CLKCR); + regs->dctrl = (uint16_t)getreg32(STM32_SDIO_DCTRL); regs->dtimer = getreg32(STM32_SDIO_DTIMER); regs->dlen = getreg32(STM32_SDIO_DLEN); regs->dcount = getreg32(STM32_SDIO_DCOUNT); @@ -731,7 +732,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) ****************************************************************************/ #ifdef CONFIG_SDIO_DMA -static void stm32_dmacallback(DMA_HANDLE handle, ubyte isr, void *arg) +static void stm32_dmacallback(DMA_HANDLE handle, uint8_t isr, void *arg) { /* FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg; */ @@ -761,9 +762,9 @@ static void stm32_dmacallback(DMA_HANDLE handle, ubyte isr, void *arg) * ****************************************************************************/ -static ubyte stm32_log2(uint16 value) +static uint8_t stm32_log2(uint16_t value) { - ubyte log2 = 0; + uint8_t log2 = 0; /* 0000 0000 0000 0001 -> return 0, * 0000 0000 0000 001x -> return 1, @@ -790,9 +791,9 @@ static ubyte stm32_log2(uint16 value) * ****************************************************************************/ -static void stm32_dataconfig(uint32 timeout, uint32 dlen, uint32 dctrl) +static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) { - uint32 regval = 0; + uint32_t regval = 0; /* Enable data path */ @@ -821,7 +822,7 @@ static void stm32_dataconfig(uint32 timeout, uint32 dlen, uint32 dctrl) static void stm32_datadisable(void) { - uint32 regval; + uint32_t regval; /* Disable the data path */ @@ -854,8 +855,8 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) { union { - uint32 w; - ubyte b[2]; + uint32_t w; + uint8_t b[2]; } data; /* Loop while there is more data to be sent and the RX FIFO is not full */ @@ -865,12 +866,12 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) { /* Is there a full word remaining in the user buffer? */ - if (priv->remaining >= sizeof(uint32)) + if (priv->remaining >= sizeof(uint32_t)) { /* Yes, transfer the word to the TX FIFO */ data.w = *priv->buffer++; - priv->remaining -= sizeof(uint32); + priv->remaining -= sizeof(uint32_t); } else { @@ -878,7 +879,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * padding with zero as necessary to extend to a full word. */ - ubyte *ptr = (ubyte *)priv->remaining; + uint8_t *ptr = (uint8_t *)priv->remaining; int i; data.w = 0; @@ -916,8 +917,8 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) { union { - uint32 w; - ubyte b[2]; + uint32_t w; + uint8_t b[2]; } data; /* Loop while there is space to store the data and there is more @@ -930,18 +931,18 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) /* Read the next word from the RX FIFO */ data.w = getreg32(STM32_SDIO_FIFO); - if (priv->remaining >= sizeof(uint32)) + if (priv->remaining >= sizeof(uint32_t)) { /* Transfer the whole word to the user buffer */ *priv->buffer++ = data.w; - priv->remaining -= sizeof(uint32); + priv->remaining -= sizeof(uint32_t); } else { /* Transfer any trailing fractional word */ - ubyte *ptr = (ubyte*)priv->buffer; + uint8_t *ptr = (uint8_t*)priv->buffer; int i; for (i = 0; i < priv->remaining; i++) @@ -965,7 +966,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) * * Input Parameters: * argc - The number of arguments (should be 1) - * arg - The argument (state structure reference cast to uint32) + * arg - The argument (state structure reference cast to uint32_t) * * Returned Value: * None @@ -975,7 +976,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -static void stm32_eventtimeout(int argc, uint32 arg) +static void stm32_eventtimeout(int argc, uint32_t arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1109,8 +1110,8 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven static int stm32_interrupt(int irq, void *context) { struct stm32_dev_s *priv = &g_sdiodev; - uint32 enabled; - uint32 pending; + uint32_t enabled; + uint32_t pending; /* Loop while there are pending interrupts. Check the SDIO status * register. Mask out all bits that don't correspond to enabled @@ -1315,9 +1316,9 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) /* DMA data transfer support */ - priv->widebus = FALSE; /* Required for DMA support */ + priv->widebus = false; /* Required for DMA support */ #ifdef CONFIG_SDIO_DMA - priv->dmamode = FALSE; /* TRUE: DMA mode transfer */ + priv->dmamode = false; /* true: DMA mode transfer */ #endif /* Configure the SDIO peripheral */ @@ -1346,7 +1347,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) * ****************************************************************************/ -static ubyte stm32_status(FAR struct sdio_dev_s *dev) +static uint8_t stm32_status(FAR struct sdio_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; return priv->cdstatus; @@ -1362,14 +1363,14 @@ static ubyte stm32_status(FAR struct sdio_dev_s *dev) * * Input Parameters: * dev - An instance of the SDIO device interface - * wide - TRUE: wide bus (4-bit) bus mode enabled + * wide - true: wide bus (4-bit) bus mode enabled * * Returned Value: * None * ****************************************************************************/ -static void stm32_widebus(FAR struct sdio_dev_s *dev, boolean wide) +static void stm32_widebus(FAR struct sdio_dev_s *dev, bool wide) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; priv->widebus = wide; @@ -1392,8 +1393,8 @@ static void stm32_widebus(FAR struct sdio_dev_s *dev, boolean wide) static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) { - uint32 clckr; - uint32 enable = 1; + uint32_t clckr; + uint32_t enable = 1; switch (rate) { @@ -1489,10 +1490,10 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) * ****************************************************************************/ -static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 arg) +static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) { - uint32 regval; - uint32 cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; + uint32_t regval; + uint32_t cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; /* Set the SDIO Argument value */ @@ -1561,14 +1562,14 @@ static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 arg) * ****************************************************************************/ -static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, +static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32 dblocksize; + uint32_t dblocksize; DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); - DEBUGASSERT(((uint32)buffer & 3) == 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); /* Reset the DPSM configuration */ @@ -1578,10 +1579,10 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, /* Save the destination buffer information for use by the interrupt handler */ - priv->buffer = (uint32*)buffer; + priv->buffer = (uint32_t*)buffer; priv->remaining = nbytes; #ifdef CONFIG_SDIO_DMA - priv->dmamode = FALSE; + priv->dmamode = false; #endif /* Then set up the SDIO data path */ @@ -1615,14 +1616,14 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, * ****************************************************************************/ -static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const ubyte *buffer, +static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, size_t nbytes) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32 dblocksize; + uint32_t dblocksize; DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); - DEBUGASSERT(((uint32)buffer & 3) == 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); /* Reset the DPSM configuration */ @@ -1632,10 +1633,10 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const ubyte *buffer, /* Save the source buffer information for use by the interrupt handler */ - priv->buffer = (uint32*)buffer; + priv->buffer = (uint32_t*)buffer; priv->remaining = nbytes; #ifdef CONFIG_SDIO_DMA - priv->dmamode = FALSE; + priv->dmamode = false; #endif /* Then set up the SDIO data path */ @@ -1721,10 +1722,10 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev) * ****************************************************************************/ -static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32 cmd) +static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { - sint32 timeout; - uint32 events; + int32_t timeout; + uint32_t events; switch (cmd & MMCSD_RESPONSE_MASK) { @@ -1794,12 +1795,12 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32 cmd) * ****************************************************************************/ -static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 *rshort) +static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { #ifdef CONFIG_DEBUG - uint32 respcmd; + uint32_t respcmd; #endif - uint32 regval; + uint32_t regval; int ret = OK; /* R1 Command response (48-bit) @@ -1863,7 +1864,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 *rs /* Check response received is of desired command */ respcmd = getreg32(STM32_SDIO_RESPCMD); - if ((ubyte)(respcmd & SDIO_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) + if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) { fdbg("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); ret = -EINVAL; @@ -1879,9 +1880,9 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 *rs return ret; } -static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 rlong[4]) +static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) { - uint32 regval; + uint32_t regval; int ret = OK; /* R2 CID, CSD register (136-bit) @@ -1932,9 +1933,9 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 rlong[4 return ret; } -static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 *rshort) +static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { - uint32 regval; + uint32_t regval; int ret = OK; /* R3 OCR (48-bit) @@ -1982,7 +1983,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 *rshor /* MMC responses not supported */ -static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 *rnotimpl) +static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) { putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR); return -ENOSYS; @@ -2016,7 +2017,7 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { struct stm32_dev_s *priv = (struct stm32_dev_s*)dev; - uint32 waitmask; + uint32_t waitmask; DEBUGASSERT(priv != NULL); @@ -2072,7 +2073,7 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev, ****************************************************************************/ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev, - uint32 timeout) + uint32_t timeout) { struct stm32_dev_s *priv = (struct stm32_dev_s*)dev; sdio_eventset_t wkupevent = 0; @@ -2103,7 +2104,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev, delay = (timeout + (MSEC_PER_TICK-1)) / MSEC_PER_TICK; ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout, - 1, (uint32)priv); + 1, (uint32_t)priv); if (ret != OK) { fdbg("ERROR: wd_start failed: %d\n", ret); @@ -2221,20 +2222,20 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev, * Name: stm32_dmasupported * * Description: - * Return TRUE if the hardware can support DMA + * Return true if the hardware can support DMA * * Input Parameters: * dev - An instance of the SDIO device interface * * Returned Value: - * TRUE if DMA is supported. + * true if DMA is supported. * ****************************************************************************/ #ifdef CONFIG_SDIO_DMA -static boolean stm32_dmasupported(FAR struct sdio_dev_s *dev) +static bool stm32_dmasupported(FAR struct sdio_dev_s *dev) { - return TRUE; + return true; } #endif @@ -2258,15 +2259,15 @@ static boolean stm32_dmasupported(FAR struct sdio_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_SDIO_DMA -static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, +static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t buflen) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32 dblocksize; + uint32_t dblocksize; int ret = -EINVAL; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); - DEBUGASSERT(((uint32)buffer & 3) == 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); /* Reset the DPSM configuration */ @@ -2281,9 +2282,9 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, /* Save the destination buffer information for use by the interrupt handler */ - priv->buffer = (uint32*)buffer; + priv->buffer = (uint32_t*)buffer; priv->remaining = buflen; - priv->dmamode = TRUE; + priv->dmamode = true; /* Then set up the SDIO data path */ @@ -2295,13 +2296,13 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, stm32_configxfrints(priv, SDIO_DMARECV_MASK); putreg32(1, SDIO_DCTRL_DMAEN_BB); - stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32)buffer, + stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer, (buflen + 3) >> 2, SDIO_RXDMA32_CONFIG); /* Start the DMA */ stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); - stm32_dmastart(priv->dma, stm32_dmacallback, priv, FALSE); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); ret = OK; } @@ -2330,14 +2331,14 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer, #ifdef CONFIG_SDIO_DMA static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, - FAR const ubyte *buffer, size_t buflen) + FAR const uint8_t *buffer, size_t buflen) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32 dblocksize; + uint32_t dblocksize; int ret = -EINVAL; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); - DEBUGASSERT(((uint32)buffer & 3) == 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); /* Reset the DPSM configuration */ @@ -2352,9 +2353,9 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Save the source buffer information for use by the interrupt handler */ - priv->buffer = (uint32*)buffer; + priv->buffer = (uint32_t*)buffer; priv->remaining = buflen; - priv->dmamode = TRUE; + priv->dmamode = true; /* Then set up the SDIO data path */ @@ -2363,7 +2364,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Configure the TX DMA */ - stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32)buffer, + stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer, (buflen + 3) >> 2, SDIO_TXDMA32_CONFIG); stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); @@ -2371,7 +2372,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Start the DMA */ - stm32_dmastart(priv->dma, stm32_dmacallback, priv, FALSE); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); /* Enable TX interrrupts */ @@ -2551,7 +2552,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) * * Input Parameters: * dev - An instance of the SDIO driver device state structure. - * cardinslot - TRUE is a card has been detected in the slot; FALSE if a + * cardinslot - true is a card has been detected in the slot; false if a * card has been removed from the slot. Only transitions * (inserted->removed or removed->inserted should be reported) * @@ -2560,10 +2561,10 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) * ****************************************************************************/ -void sdio_mediachange(FAR struct sdio_dev_s *dev, boolean cardinslot) +void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - ubyte cdstatus; + uint8_t cdstatus; irqstate_t flags; /* Update card status */ @@ -2598,14 +2599,14 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, boolean cardinslot) * * Input Parameters: * dev - An instance of the SDIO driver device state structure. - * wrprotect - TRUE is a card is writeprotected. + * wrprotect - true is a card is writeprotected. * * Returned Values: * None * ****************************************************************************/ -void sdio_wrprotect(FAR struct sdio_dev_s *dev, boolean wrprotect) +void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; irqstate_t flags; diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index c94f08b03..2ff783b0a 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -38,8 +38,10 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> #include <unistd.h> #include <semaphore.h> #include <string.h> @@ -161,33 +163,33 @@ struct up_dev_s { - uint32 usartbase; /* Base address of USART registers */ - uint32 apbclock; /* PCLK 1 or 2 frequency */ - uint32 baud; /* Configured baud */ - uint16 ie; /* Saved interrupt mask bits value */ - uint16 sr; /* Saved status bits */ - ubyte irq; /* IRQ associated with this USART */ - ubyte parity; /* 0=none, 1=odd, 2=even */ - ubyte bits; /* Number of bits (7 or 8) */ - boolean stopbits2; /* TRUE: Configure with 2 stop bits instead of 1 */ + uint32_t usartbase; /* Base address of USART registers */ + uint32_t apbclock; /* PCLK 1 or 2 frequency */ + uint32_t baud; /* Configured baud */ + uint16_t ie; /* Saved interrupt mask bits value */ + uint16_t sr; /* Saved status bits */ + uint8_t irq; /* IRQ associated with this USART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32 *status); -static void up_rxint(struct uart_dev_s *dev, boolean enable); -static boolean up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, boolean enable); -static boolean up_txready(struct uart_dev_s *dev); +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); /**************************************************************************** * Private Variables @@ -325,7 +327,7 @@ static uart_dev_t g_usart3port = * Name: up_serialin ****************************************************************************/ -static inline uint32 up_serialin(struct up_dev_s *priv, int offset) +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -334,7 +336,7 @@ static inline uint32 up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32 value) +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) { putreg16(value, priv->usartbase + offset); } @@ -343,9 +345,9 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, uint32 value) * Name: up_restoreusartint ****************************************************************************/ -static void up_restoreusartint(struct up_dev_s *priv, uint16 ie) +static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { - uint32 cr; + uint32_t cr; /* Save the interrupt mask */ @@ -368,12 +370,12 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16 ie) * Name: up_disableusartint ****************************************************************************/ -static inline void up_disableusartint(struct up_dev_s *priv, uint16 *ie) +static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { if (ie) { - uint32 cr1; - uint32 cr3; + uint32_t cr1; + uint32_t cr3; /* USART interrupts: * @@ -422,11 +424,11 @@ static int up_setup(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; #ifdef CONFIG_SUPPRESS_USART_CONFIG - uint32 uartdiv32; - uint32 mantissa; - uint32 fraction; - uint32 brr; - uint32 regval; + uint32_t uartdiv32; + uint32_t mantissa; + uint32_t fraction; + uint32_t brr; + uint32_t regval; /* Note: The logic here depends on the fact that that the USART module * was enabled and the pins were configured in stm32_lowsetup(). @@ -535,7 +537,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint32 regval; + uint32_t regval; /* Disable all interrupts */ @@ -616,7 +618,7 @@ static int up_interrupt(int irq, void *context) struct uart_dev_s *dev = NULL; struct up_dev_s *priv; int passes; - boolean handled; + bool handled; #ifdef CONFIG_STM32_USART1 if (g_usart1priv.irq == irq) @@ -648,10 +650,10 @@ static int up_interrupt(int irq, void *context) * until we have been looping for a long time. */ - handled = TRUE; + handled = true; for (passes = 0; passes < 256 && handled; passes++) { - handled = FALSE; + handled = false; /* Get the masked USART status and clear the pending interrupts. */ @@ -686,7 +688,7 @@ static int up_interrupt(int irq, void *context) /* Received data ready... process incoming bytes */ uart_recvchars(dev); - handled = TRUE; + handled = true; } /* Handle outgoing, transmit bytes */ @@ -696,7 +698,7 @@ static int up_interrupt(int irq, void *context) /* Transmit data regiser empty ... process outgoing bytes */ uart_xmitchars(dev); - handled = TRUE; + handled = true; } } return OK; @@ -739,7 +741,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags = irqsave(); - uint32 cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); + uint32_t cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN); irqrestore(flags); } @@ -749,7 +751,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { irqstate_t flags; flags = irqsave(); - uint32 cr1 = up_serialin(priv, STM32_USART_CR2_OFFSET); + uint32_t cr1 = up_serialin(priv, STM32_USART_CR2_OFFSET); up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN); irqrestore(flags); } @@ -774,10 +776,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32 *status) +static int up_receive(struct uart_dev_s *dev, uint32_t *status) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint32 dr; + uint32_t dr; /* Get the Rx byte */ @@ -801,10 +803,10 @@ static int up_receive(struct uart_dev_s *dev, uint32 *status) * ****************************************************************************/ -static void up_rxint(struct uart_dev_s *dev, boolean enable) +static void up_rxint(struct uart_dev_s *dev, bool enable) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16 ie; + uint16_t ie; /* USART receive interrupts: * @@ -850,11 +852,11 @@ static void up_rxint(struct uart_dev_s *dev, boolean enable) * Name: up_rxavailable * * Description: - * Return TRUE if the receive register is not empty + * Return true if the receive register is not empty * ****************************************************************************/ -static boolean up_rxavailable(struct uart_dev_s *dev) +static bool up_rxavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; return ((up_serialin(priv, STM32_USART_SR_OFFSET) & USART_SR_RXNE) != 0); @@ -871,7 +873,7 @@ static boolean up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_serialout(priv, STM32_USART_DR_OFFSET, (uint32)ch); + up_serialout(priv, STM32_USART_DR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -882,7 +884,7 @@ static void up_send(struct uart_dev_s *dev, int ch) * ****************************************************************************/ -static void up_txint(struct uart_dev_s *dev, boolean enable) +static void up_txint(struct uart_dev_s *dev, bool enable) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; irqstate_t flags; @@ -924,11 +926,11 @@ static void up_txint(struct uart_dev_s *dev, boolean enable) * Name: up_txready * * Description: - * Return TRUE if the tranmsit data register is empty + * Return true if the tranmsit data register is empty * ****************************************************************************/ -static boolean up_txready(struct uart_dev_s *dev) +static bool up_txready(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; return ((up_serialin(priv, STM32_USART_SR_OFFSET) & USART_SR_TXE) != 0); @@ -967,7 +969,7 @@ void up_earlyserialinit(void) /* Configuration whichever one is the console */ #ifdef HAVE_CONSOLE - CONSOLE_DEV.isconsole = TRUE; + CONSOLE_DEV.isconsole = true; up_setup(&CONSOLE_DEV); #endif } @@ -1012,7 +1014,7 @@ int up_putc(int ch) { #ifdef HAVE_CONSOLE struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; - uint16 ie; + uint16_t ie; up_disableusartint(priv, &ie); diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.c b/nuttx/arch/arm/src/stm32/stm32_spi.c index 2ca8989c8..bdea7da37 100755 --- a/nuttx/arch/arm/src/stm32/stm32_spi.c +++ b/nuttx/arch/arm/src/stm32/stm32_spi.c @@ -53,7 +53,7 @@ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * - ************************************************************************************/ + ****************************************************c********************************/ /************************************************************************************ * Included Files @@ -61,6 +61,9 @@ #include <nuttx/config.h> +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> #include <semaphore.h> #include <errno.h> #include <debug.h> @@ -114,20 +117,20 @@ struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ - uint32 spibase; /* SPIn base address */ - uint32 spiclock; /* Clocking for the SPI module */ - uint32 frequency; /* Requested clock frequency */ - uint32 actual; /* Actual clock frequency */ - ubyte nbits; /* Width of work in bits (8 or 16) */ - ubyte mode; /* Mode 0,1,2,3 */ + uint32_t spibase; /* SPIn base address */ + uint32_t spiclock; /* Clocking for the SPI module */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of work in bits (8 or 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ #ifdef CONFIG_STM32_SPI_INTERRUPTS - ubyte spiirq; /* SPI IRQ number */ + uint8_t spiirq; /* SPI IRQ number */ #endif #ifdef CONFIG_STM32_SPI_DMA - volatile ubyte rxresult; /* Result of the RX DMA */ - volatile ubyte txresult; /* Result of the RX DMA */ - ubyte rxch; /* The RX DMA channel number */ - ubyte txch; /* The TX DMA channel number */ + volatile uint8_t rxresult; /* Result of the RX DMA */ + volatile uint8_t txresult; /* Result of the RX DMA */ + uint8_t rxch; /* The RX DMA channel number */ + uint8_t txch; /* The TX DMA channel number */ DMA_HANDLE rxdma; /* DMA channel handle for RX transfers */ DMA_HANDLE txdma; /* DMA channel handle for TX transfers */ sem_t rxsem; /* Wait for RX DMA to complete */ @@ -142,49 +145,49 @@ struct stm32_spidev_s /* Helpers */ -static inline uint16 spi_getreg(FAR struct stm32_spidev_s *priv, ubyte offset); -static inline void spi_putreg(FAR struct stm32_spidev_s *priv, ubyte offset, - uint16 value); -static inline uint16 spi_readword(FAR struct stm32_spidev_s *priv); -static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16 byte); -static inline boolean spi_16bitmode(FAR struct stm32_spidev_s *priv); +static inline uint16_t spi_getreg(FAR struct stm32_spidev_s *priv, uint8_t offset); +static inline void spi_putreg(FAR struct stm32_spidev_s *priv, uint8_t offset, + uint16_t value); +static inline uint16_t spi_readword(FAR struct stm32_spidev_s *priv); +static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16_t byte); +static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxwait(FAR struct stm32_spidev_s *priv); -static void spi_dmatxwait(FAR struct stm32_spidev_s *priv); -static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv); -static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv); -static void spi_dmarxcallback(DMA_HANDLE handle, ubyte isr, void *arg); -static void spi_dmatxcallback(DMA_HANDLE handle, ubyte isr, void *arg); -static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, - FAR void *rxbuffer, FAR void *rxdummy, size_t nwords); -static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, - FAR const void *txbuffer, FAR const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv); -static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv); +static void spi_dmarxwait(FAR struct stm32_spidev_s *priv); +static void spi_dmatxwait(FAR struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv); +static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); +static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); +static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, + FAR void *rxbuffer, FAR void *rxdummy, size_t nwords); +static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, + FAR const void *txbuffer, FAR const void *txdummy, size_t nwords); +static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv); #endif /* SPI methods */ -static int spi_lock(FAR struct spi_dev_s *dev, boolean lock); -static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency); -static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); -static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); -static uint16 spi_send(FAR struct spi_dev_s *dev, uint16 wd); -static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - FAR void *rxbuffer, size_t nwords); +static int spi_lock(FAR struct spi_dev_s *dev, bool lock); +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); +static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); +static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd); +static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); #ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - size_t nwords); -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, - size_t nwords); +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, + size_t nwords); #endif /* Initialization */ -static void spi_portinitialize(FAR struct stm32_spidev_s *priv); +static void spi_portinitialize(FAR struct stm32_spidev_s *priv); /************************************************************************************ * Private Data @@ -315,7 +318,7 @@ static struct stm32_spidev_s g_spi3dev = * ************************************************************************************/ -static inline uint16 spi_getreg(FAR struct stm32_spidev_s *priv, ubyte offset) +static inline uint16_t spi_getreg(FAR struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); } @@ -336,7 +339,7 @@ static inline uint16 spi_getreg(FAR struct stm32_spidev_s *priv, ubyte offset) * ************************************************************************************/ -static inline void spi_putreg(FAR struct stm32_spidev_s *priv, ubyte offset, uint16 value) +static inline void spi_putreg(FAR struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); } @@ -355,7 +358,7 @@ static inline void spi_putreg(FAR struct stm32_spidev_s *priv, ubyte offset, uin * ************************************************************************************/ -static inline uint16 spi_readword(FAR struct stm32_spidev_s *priv) +static inline uint16_t spi_readword(FAR struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -381,7 +384,7 @@ static inline uint16 spi_readword(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16 word) +static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -402,11 +405,11 @@ static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16 word) * priv - Device-specific state data * * Returned Value: - * TRUE: 16-bit mode, FALSE: 8-bit mode + * true: 16-bit mode, false: 8-bit mode * ************************************************************************************/ -static inline boolean spi_16bitmode(FAR struct stm32_spidev_s *priv) +static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv) { return ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_DFF) != 0); } @@ -487,7 +490,7 @@ static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv) ************************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxcallback(DMA_HANDLE handle, ubyte isr, void *arg) +static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg; priv->rxresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ @@ -504,7 +507,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, ubyte isr, void *arg) ************************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxcallback(DMA_HANDLE handle, ubyte isr, void *arg) +static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg; priv->txresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ @@ -524,7 +527,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, ubyte isr, void *arg) static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer, FAR void *rxdummy, size_t nwords) { - uint32 ccr; + uint32_t ccr; /* 8- or 16-bit mode? */ @@ -559,7 +562,7 @@ static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer, /* Configure the RX DMA */ - stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32)rxbuffer, nwords, ccr); + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, ccr); } #endif @@ -575,7 +578,7 @@ static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer, static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbuffer, FAR const void *txdummy, size_t nwords) { - uint32 ccr; + uint32_t ccr; /* 8- or 16-bit mode? */ @@ -610,7 +613,7 @@ static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbu /* Setup the TX DMA */ - stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET,(uint32)txbuffer, nwords, ccr); + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET,(uint32_t)txbuffer, nwords, ccr); } #endif @@ -625,7 +628,7 @@ static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbu #ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv) { - stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, FALSE); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -640,7 +643,7 @@ static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv) #ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv) { - stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, FALSE); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -660,9 +663,9 @@ static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16 setbits, uint16 clrbits) +static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { - uint16 cr1; + uint16_t cr1; cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET); cr1 &= ~clrbits; cr1 |= setbits; @@ -683,14 +686,14 @@ static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16 setbits, uint1 * * Input Parameters: * dev - Device-specific state data - * lock - TRUE: Lock spi bus, FALSE: unlock SPI bus + * lock - true: Lock spi bus, false: unlock SPI bus * * Returned Value: * None * ****************************************************************************/ -static int spi_lock(FAR struct spi_dev_s *dev, boolean lock) +static int spi_lock(FAR struct spi_dev_s *dev, bool lock) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; @@ -729,11 +732,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, boolean lock) * ************************************************************************************/ -static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency) +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; - uint16 setbits; - uint32 actual; + uint16_t setbits; + uint32_t actual; /* Has the frequency changed? */ @@ -823,8 +826,8 @@ static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency) static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; - uint16 setbits; - uint16 clrbits; + uint16_t setbits; + uint16_t clrbits; /* Has the mode changed? */ @@ -881,8 +884,8 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; - uint16 setbits; - uint16 clrbits; + uint16_t setbits; + uint16_t clrbits; /* Has the number of bits changed? */ @@ -927,7 +930,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) * ************************************************************************************/ -static uint16 spi_send(FAR struct spi_dev_s *dev, uint16 wd) +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; @@ -950,7 +953,7 @@ static uint16 spi_send(FAR struct spi_dev_s *dev, uint16 wd) * nwords - the length of data to be exchaned in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into ubytes; if nbits >8, the data is packed into uint16's + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's * * Returned Value: * None @@ -970,9 +973,9 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, { /* 16-bit mode */ - const uint16 *src = (const uint16*)txbuffer;; - uint16 *dest = (uint16*)rxbuffer; - uint16 word; + const uint16_t *src = (const uint16_t*)txbuffer;; + uint16_t *dest = (uint16_t*)rxbuffer; + uint16_t word; while (nwords-- > 0) { @@ -1003,9 +1006,9 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, { /* 8-bit mode */ - const ubyte *src = (const ubyte*)txbuffer;; - ubyte *dest = (ubyte*)rxbuffer; - ubyte word; + const uint8_t *src = (const uint8_t*)txbuffer;; + uint8_t *dest = (uint8_t*)rxbuffer; + uint8_t word; while (nwords-- > 0) { @@ -1022,7 +1025,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, /* Exchange one word */ - word = (ubyte)spi_send(dev, (uint16)word); + word = (uint8_t)spi_send(dev, (uint16_t)word); /* Is there a buffer to receive the return value? */ @@ -1048,7 +1051,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, * nwords - the length of data to be exchaned in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into ubytes; if nbits >8, the data is packed into uint16's + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's * * Returned Value: * None @@ -1060,8 +1063,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; - uint16 rxdummy = 0xffff; - uint16 txdummy; + uint16_t rxdummy = 0xffff; + uint16_t txdummy; DEBUGASSERT(priv && priv->spibase); @@ -1094,7 +1097,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, * nwords - the length of data to send from the buffer in number of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into ubytes; if nbits >8, the data is packed into uint16's + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's * * Returned Value: * None @@ -1120,7 +1123,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, si * nwords - the length of data that can be received in the buffer in number * of words. The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into ubytes; if nbits >8, the data is packed into uint16's + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's * * Returned Value: * None @@ -1150,8 +1153,8 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t static void spi_portinitialize(FAR struct stm32_spidev_s *priv) { - uint16 setbits; - uint16 clrbits; + uint16_t setbits; + uint16_t clrbits; /* Configure CR1. Default configuration: * Mode 0: CPHA=0 and CPOL=0 @@ -1234,7 +1237,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) #ifdef CONFIG_STM32_SPI1 if (port == 0) { - uint32 mapr; + uint32_t mapr; /* Select SPI1 */ diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.h b/nuttx/arch/arm/src/stm32/stm32_spi.h index 21d95d01d..2d4721745 100755 --- a/nuttx/arch/arm/src/stm32/stm32_spi.h +++ b/nuttx/arch/arm/src/stm32/stm32_spi.h @@ -1,158 +1,158 @@ -/************************************************************************************ - * arch/arm/src/stm32/stm32_spi.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_STC_STM32_STM32_SPI_H -#define __ARCH_ARM_STC_STM32_STM32_SPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> -#include <sys/types.h> +/************************************************************************************
+ * arch/arm/src/stm32/stm32_spi.h
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_STC_STM32_STM32_SPI_H
+#define __ARCH_ARM_STC_STM32_STM32_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
#include "chip.h"
- -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ - -/* Register Addresses ***************************************************************/ - -#if STM32_NSPI > 0 -# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) -#endif - -#if STM32_NSPI > 1 -# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) -#endif - -/* Register Bitfield Definitions ****************************************************/ - -/* SPI Control Register 1 */ - -#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ -#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ -#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ -#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ -#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) -# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ -# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ -# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ -# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ -# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ -# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ -# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ -# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ -#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ -#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ -#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ -#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ -#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ -#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */ -#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ -#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ - -/* SPI Control Register 2 */ - -#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ -#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ - -/* SPI status register */ - -#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ -#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ -#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ -#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ -#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ -#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */ +
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
+#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
+#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
+#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
+#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
+#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
+#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NSPI > 0
+# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
+# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
+# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
+# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
+# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
+# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
+# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32_NSPI > 1
+# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
+# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
+# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
+# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
+# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
+# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
+# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* SPI Control Register 1 */
+
+#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
+#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
+#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
+#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
+#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
+# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
+# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
+# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
+# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
+# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
+# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
+# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
+# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
+#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
+#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
+#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
+#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
+#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
+#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
+#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
+#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
+
+/* SPI Control Register 2 */
+
+#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
+#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
+#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
+#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
+
+/* SPI status register */
+
+#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
+#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
+#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
+#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
+#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
+#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */
diff --git a/nuttx/arch/arm/src/stm32/stm32_start.c b/nuttx/arch/arm/src/stm32/stm32_start.c index 6b9ed1495..7ed3c0851 100644 --- a/nuttx/arch/arm/src/stm32/stm32_start.c +++ b/nuttx/arch/arm/src/stm32/stm32_start.c @@ -39,8 +39,8 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <stdint.h> #include <assert.h> #include <debug.h> @@ -94,8 +94,8 @@ void __start(void) { - const uint32 *src; - uint32 *dest; + const uint32_t *src; + uint32_t *dest; /* Configure the uart so that we can get debug output as soon as possible */ diff --git a/nuttx/arch/arm/src/stm32/stm32_tim.h b/nuttx/arch/arm/src/stm32/stm32_tim.h index 2e665b55f..21b37bb72 100644 --- a/nuttx/arch/arm/src/stm32/stm32_tim.h +++ b/nuttx/arch/arm/src/stm32/stm32_tim.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_timerisr.c b/nuttx/arch/arm/src/stm32/stm32_timerisr.c index b784fd2ab..93cca02ac 100644 --- a/nuttx/arch/arm/src/stm32/stm32_timerisr.c +++ b/nuttx/arch/arm/src/stm32/stm32_timerisr.c @@ -38,7 +38,8 @@ ****************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + +#include <stdint.h> #include <time.h> #include <debug.h> #include <nuttx/arch.h> @@ -105,7 +106,7 @@ * ****************************************************************************/ -int up_timerisr(int irq, uint32 *regs) +int up_timerisr(int irq, uint32_t *regs) { /* Process timer interrupt */ @@ -124,7 +125,7 @@ int up_timerisr(int irq, uint32 *regs) void up_timerinit(void) { - uint32 regval; + uint32_t regval; /* Set the SysTick interrupt to the default priority */ diff --git a/nuttx/arch/arm/src/stm32/stm32_uart.h b/nuttx/arch/arm/src/stm32/stm32_uart.h index 6a1213ca1..1562296fa 100755 --- a/nuttx/arch/arm/src/stm32/stm32_uart.h +++ b/nuttx/arch/arm/src/stm32/stm32_uart.h @@ -1,211 +1,211 @@ -/************************************************************************************ - * arch/arm/src/stm32/stm32_uart.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H -#define __ARCH_ARM_STC_STM32_STM32_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - +/************************************************************************************
+ * arch/arm/src/stm32/stm32_uart.h
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H
+#define __ARCH_ARM_STC_STM32_STM32_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
#include <nuttx/config.h>
-#include <sys/types.h>
+
#include "chip.h"
- -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses ***************************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 0 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ****************************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 6) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 7) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_GT_SHIFT (8) /* Bits 15-8: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) -#define USART_GTPR_PSC_SHIFT (0) /* Bits 7:0 [7:0]: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */ +
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
+#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
+#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
+#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
+#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
+#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
+#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NUSART > 0
+# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
+# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
+# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
+# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
+# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
+# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
+# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 1
+# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
+# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
+# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
+# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
+# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
+# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
+# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 0
+# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
+# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
+# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
+# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
+# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
+# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
+# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 3
+# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
+# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
+# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
+# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
+# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
+# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
+#endif
+
+#if STM32_NUSART > 4
+# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
+# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
+# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
+# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
+# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
+# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Status register */
+
+#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
+#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
+#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
+#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
+#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
+#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
+#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
+#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
+#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
+#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
+
+#define USART_SR_ALLBITS (0x03ff)
+#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
+
+/* Data register */
+
+#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
+#define USART_DR_MASK (0xff << USART_DR_SHIFT)
+
+/* Baud Rate Register */
+
+#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
+#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
+#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
+#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
+
+/* Control register 1 */
+
+#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
+#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
+#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
+#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
+#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
+#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
+#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
+#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
+#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
+#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
+#define USART_CR1_M (1 << 12) /* Bit 12: word length */
+#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
+
+#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
+
+/* Control register 2 */
+
+#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
+#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
+#define USART_CR2_LBDL (1 << 6) /* Bit 5: LIN Break Detection Length */
+#define USART_CR2_LBDIE (1 << 7) /* Bit 6: LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
+#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
+#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
+#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
+#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
+#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
+# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
+# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
+# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
+# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
+#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
+
+/* Control register 3 */
+
+#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
+#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
+#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
+#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
+#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
+#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
+#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
+#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
+#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
+#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
+#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
+
+/* Guard time and prescaler register */
+
+#define USART_GTPR_GT_SHIFT (8) /* Bits 15-8: Guard time value */
+#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
+#define USART_GTPR_PSC_SHIFT (0) /* Bits 7:0 [7:0]: Prescaler value */
+#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */
diff --git a/nuttx/arch/arm/src/stm32/stm32_usbdev.c b/nuttx/arch/arm/src/stm32/stm32_usbdev.c index 9dd75cf97..7fbcd3ef7 100644 --- a/nuttx/arch/arm/src/stm32/stm32_usbdev.c +++ b/nuttx/arch/arm/src/stm32/stm32_usbdev.c @@ -44,6 +44,8 @@ #include <nuttx/config.h> #include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> #include <stdlib.h> #include <string.h> #include <errno.h> @@ -267,15 +269,15 @@ enum stm32_rsmstate_e union wb_u { - uint16 w; - ubyte b[2]; + uint16_t w; + uint8_t b[2]; }; /* A container for a request so that the request make be retained in a list */ struct stm32_req_s { - struct usbdev_req_s req; /* Standard USB request */ + struct usbdev_req_s req; /* Standard USB request */ struct stm32_req_s *flink; /* Supports a singly linked list */ }; @@ -295,11 +297,11 @@ struct stm32_ep_s struct stm32_usbdev_s *dev; /* Reference to private driver data */ struct stm32_req_s *head; /* Request list for this endpoint */ struct stm32_req_s *tail; - ubyte bufno; /* Allocated buffer number */ - ubyte stalled:1; /* TRUE: Endpoint is stalled */ - ubyte halted:1; /* TRUE: Endpoint feature halted */ - ubyte txbusy:1; /* TRUE: TX endpoint FIFO full */ - ubyte txnullpkt:1; /* Null packet needed at end of transfer */ + uint8_t bufno; /* Allocated buffer number */ + uint8_t stalled:1; /* true: Endpoint is stalled */ + uint8_t halted:1; /* true: Endpoint feature halted */ + uint8_t txbusy:1; /* true: TX endpoint FIFO full */ + uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ }; struct stm32_usbdev_s @@ -318,16 +320,16 @@ struct stm32_usbdev_s /* STM32-specific fields */ struct usb_ctrlreq_s ctrl; /* Last EP0 request */ - ubyte devstate; /* Driver state (see enum stm32_devstate_e) */ - ubyte rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ - ubyte nesofs; /* ESOF counter (for resume support) */ - ubyte rxpending:1; /* 1: OUT data in PMA, but no read requests */ - ubyte selfpowered:1; /* 1: Device is self powered */ - ubyte epavail; /* Bitset of available endpoints */ - ubyte bufavail; /* Bitset of available buffers */ - uint16 rxstatus; /* Saved during interrupt processing */ - uint16 txstatus; /* " " " " " " " " */ - uint16 imask; /* Current interrupt mask */ + uint8_t devstate; /* Driver state (see enum stm32_devstate_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ + uint8_t nesofs; /* ESOF counter (for resume support) */ + uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t epavail; /* Bitset of available endpoints */ + uint8_t bufavail; /* Bitset of available buffers */ + uint16_t rxstatus; /* Saved during interrupt processing */ + uint16_t txstatus; /* " " " " " " " " */ + uint16_t imask; /* Current interrupt mask */ /* The endpoint list */ @@ -341,8 +343,8 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG) -static uint16 stm32_getreg(uint32 addr); -static void stm32_putreg(uint16 val, uint32 addr); +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); static void stm32_dumpep(int epno); #else @@ -355,42 +357,42 @@ static void stm32_dumpep(int epno); /* Low-Level Helpers ********************************************************/ static inline void - stm32_seteptxcount(ubyte epno, uint16 count); + stm32_seteptxcount(uint8_t epno, uint16_t count); static inline void - stm32_seteptxaddr(ubyte epno, uint16 addr); -static inline uint16 - stm32_geteptxaddr(ubyte epno); -static void stm32_seteprxcount(ubyte epno, uint16 count); -static inline uint16 - stm32_geteprxcount(ubyte epno); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); +static inline uint16_t + stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); +static inline uint16_t + stm32_geteprxcount(uint8_t epno); static inline void - stm32_seteprxaddr(ubyte epno, uint16 addr); -static inline uint16 - stm32_geteprxaddr(ubyte epno); + stm32_seteprxaddr(uint8_t epno, uint16_t addr); +static inline uint16_t + stm32_geteprxaddr(uint8_t epno); static inline void - stm32_setepaddress(ubyte epno, uint16 addr); + stm32_setepaddress(uint8_t epno, uint16_t addr); static inline void - stm32_seteptype(ubyte epno, uint16 type); + stm32_seteptype(uint8_t epno, uint16_t type); static inline void - stm32_seteptxaddr(ubyte epno, uint16 addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline void - stm32_setstatusout(ubyte epno); + stm32_setstatusout(uint8_t epno); static inline void - stm32_clrstatusout(ubyte epno); -static void stm32_clrrxdtog(ubyte epno); -static void stm32_clrtxdtog(ubyte epno); -static void stm32_clrepctrrx(ubyte epno); -static void stm32_clrepctrtx(ubyte epno); -static void stm32_seteptxstatus(ubyte epno, uint16 state); -static void stm32_seteprxstatus(ubyte epno, uint16 state); -static inline uint16 - stm32_geteptxstatus(ubyte epno); -static inline uint16 - stm32_geteprxstatus(ubyte epno); -static uint16 stm32_eptxstalled(ubyte epno); -static uint16 stm32_eprxstalled(ubyte epno); -static void stm32_setimask(struct stm32_usbdev_s *priv, uint16 setbits, - uint16 clrbits); + stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); +static inline uint16_t + stm32_geteptxstatus(uint8_t epno); +static inline uint16_t + stm32_geteprxstatus(uint8_t epno); +static uint16_t stm32_eptxstalled(uint8_t epno); +static uint16_t stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, + uint16_t clrbits); /* Suspend/Resume Helpers ***************************************************/ @@ -400,20 +402,20 @@ static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; /* Request Helpers **********************************************************/ -static void stm32_copytopma(const ubyte *buffer, uint16 pma, - uint16 nbytes); +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, + uint16_t nbytes); static inline void - stm32_copyfrompma(ubyte *buffer, uint16 pma, uint16 nbytes); + stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes); static struct stm32_req_s * stm32_rqdequeue(struct stm32_ep_s *privep); static void stm32_rqenqueue(struct stm32_ep_s *privep, struct stm32_req_s *req); static inline void stm32_abortrequest(struct stm32_ep_s *privep, - struct stm32_req_s *privreq, sint16 result); -static void stm32_reqcomplete(struct stm32_ep_s *privep, sint16 result); + struct stm32_req_s *privreq, int16_t result); +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); static void stm32_epwrite(struct stm32_usbdev_s *buf, - struct stm32_ep_s *privep, const ubyte *data, uint32 nbytes); + struct stm32_ep_s *privep, const uint8_t *data, uint32_t nbytes); static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep); static int stm32_rdrequest(struct stm32_usbdev_s *priv, @@ -423,13 +425,13 @@ static void stm32_cancelrequests(struct stm32_ep_s *privep); /* Interrupt level processing ***********************************************/ static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); -static void stm32_epdone(struct stm32_usbdev_s *priv, ubyte epno); -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, ubyte value); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); static void stm32_ep0setup(struct stm32_usbdev_s *priv); static void stm32_ep0out(struct stm32_usbdev_s *priv); static void stm32_ep0in(struct stm32_usbdev_s *priv); static inline void - stm32_ep0done(struct stm32_usbdev_s *priv, uint16 istr); + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); static void stm32_lptransfer(struct stm32_usbdev_s *priv); static int stm32_hpinterrupt(int irq, void *context); static int stm32_lpinterrupt(int irq, void *context); @@ -437,11 +439,11 @@ static int stm32_lpinterrupt(int irq, void *context); /* Endpoint helpers *********************************************************/ static inline struct stm32_ep_s * - stm32_epreserve(struct stm32_usbdev_s *priv, ubyte epset); + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); static inline void stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep); -static inline boolean +static inline bool stm32_epreserved(struct stm32_usbdev_s *priv, int epno); static int stm32_epallocpma(struct stm32_usbdev_s *priv); static inline void @@ -451,7 +453,7 @@ static inline void /* Endpoint operations ******************************************************/ static int stm32_epconfigure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, boolean last); + const struct usb_epdesc_s *desc, bool last); static int stm32_epdisable(struct usbdev_ep_s *ep); static struct usbdev_req_s * stm32_epallocreq(struct usbdev_ep_s *ep); @@ -461,17 +463,17 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); /* USB device controller operations *****************************************/ static struct usbdev_ep_s * - stm32_allocep(struct usbdev_s *dev, ubyte epno, boolean in, - ubyte eptype); + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + uint8_t eptype); static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); static int stm32_getframe(struct usbdev_s *dev); static int stm32_wakeup(struct usbdev_s *dev); -static int stm32_selfpowered(struct usbdev_s *dev, boolean selfpowered); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); /* Initialization/Reset *****************************************************/ @@ -525,15 +527,15 @@ static const struct usbdev_ops_s g_devops = ****************************************************************************/ #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG) -static uint16 stm32_getreg(uint32 addr) +static uint16_t stm32_getreg(uint32_t addr) { - static uint32 prevaddr = 0; - static uint16 preval = 0; - static uint32 count = 0; + static uint32_t prevaddr = 0; + static uint16_t preval = 0; + static uint32_t count = 0; /* Read the value from the register */ - uint16 val = getreg16(addr); + uint16_t val = getreg16(addr); /* Is this the same value that we read from the same register last time? * Are we polling the register? If so, suppress some of the output. @@ -583,7 +585,7 @@ static uint16 stm32_getreg(uint32 addr) ****************************************************************************/ #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG) -static void stm32_putreg(uint16 val, uint32 addr) +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -602,7 +604,7 @@ static void stm32_putreg(uint16 val, uint32 addr) #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG) static void stm32_dumpep(int epno) { - uint32 addr; + uint32_t addr; /* Common registers */ @@ -645,9 +647,9 @@ static void stm32_dumpep(int epno) #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG) static void stm32_checksetup(void) { - uint32 cfgr = getreg32(STM32_RCC_CFGR); - uint32 apb1rstr = getreg32(STM32_RCC_APB1RSTR); - uint32 apb1enr = getreg32(STM32_RCC_APB1ENR); + uint32_t cfgr = getreg32(STM32_RCC_CFGR); + uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR); + uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR); lldbg("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr); @@ -666,9 +668,9 @@ static void stm32_checksetup(void) * Name: stm32_seteptxcount ****************************************************************************/ -static inline void stm32_seteptxcount(ubyte epno, uint16 count) +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) { - volatile uint32 *epaddr = (uint32*)STM32_USB_COUNT_TX(epno); + volatile uint32_t *epaddr = (uint32_t*)STM32_USB_COUNT_TX(epno); *epaddr = count; } @@ -676,9 +678,9 @@ static inline void stm32_seteptxcount(ubyte epno, uint16 count) * Name: stm32_seteptxaddr ****************************************************************************/ -static inline void stm32_seteptxaddr(ubyte epno, uint16 addr) +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) { - volatile uint32 *txaddr = (uint32*)STM32_USB_ADDR_TX(epno); + volatile uint32_t *txaddr = (uint32_t*)STM32_USB_ADDR_TX(epno); *txaddr = addr; } @@ -686,21 +688,21 @@ static inline void stm32_seteptxaddr(ubyte epno, uint16 addr) * Name: stm32_geteptxaddr ****************************************************************************/ -static inline uint16 stm32_geteptxaddr(ubyte epno) +static inline uint16_t stm32_geteptxaddr(uint8_t epno) { - volatile uint32 *txaddr = (uint32*)STM32_USB_ADDR_TX(epno); - return (uint16)*txaddr; + volatile uint32_t *txaddr = (uint32_t*)STM32_USB_ADDR_TX(epno); + return (uint16_t)*txaddr; } /**************************************************************************** * Name: stm32_seteprxcount ****************************************************************************/ -static void stm32_seteprxcount(ubyte epno, uint16 count) +static void stm32_seteprxcount(uint8_t epno, uint16_t count) { - volatile uint32 *epaddr = (uint32*)STM32_USB_COUNT_RX(epno); - uint32 rxcount = 0; - uint16 nblocks; + volatile uint32_t *epaddr = (uint32_t*)STM32_USB_COUNT_RX(epno); + uint32_t rxcount = 0; + uint16_t nblocks; /* The upper bits of the RX COUNT value contain the size of allocated * RX buffer. This is based on a block size of 2 or 32: @@ -726,7 +728,7 @@ static void stm32_seteprxcount(ubyte epno, uint16 count) nblocks = (count >> 5) - 1 ; DEBUGASSERT(nblocks <= 0x0f); - rxcount = (uint32)((nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE); + rxcount = (uint32_t)((nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE); } else if (count > 0) { @@ -734,7 +736,7 @@ static void stm32_seteprxcount(ubyte epno, uint16 count) nblocks = (count + 1) >> 1; DEBUGASSERT(nblocks > 0 && nblocks < 0x1f); - rxcount = (uint32)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); + rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); } *epaddr = rxcount; } @@ -743,9 +745,9 @@ static void stm32_seteprxcount(ubyte epno, uint16 count) * Name: stm32_geteprxcount ****************************************************************************/ -static inline uint16 stm32_geteprxcount(ubyte epno) +static inline uint16_t stm32_geteprxcount(uint8_t epno) { - volatile uint32 *epaddr = (uint32*)STM32_USB_COUNT_RX(epno); + volatile uint32_t *epaddr = (uint32_t*)STM32_USB_COUNT_RX(epno); return (*epaddr) & USB_COUNT_RX_MASK; } @@ -753,9 +755,9 @@ static inline uint16 stm32_geteprxcount(ubyte epno) * Name: stm32_seteprxaddr ****************************************************************************/ -static inline void stm32_seteprxaddr(ubyte epno, uint16 addr) +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) { - volatile uint32 *rxaddr = (uint32*)STM32_USB_ADDR_RX(epno); + volatile uint32_t *rxaddr = (uint32_t*)STM32_USB_ADDR_RX(epno); *rxaddr = addr; } @@ -763,20 +765,20 @@ static inline void stm32_seteprxaddr(ubyte epno, uint16 addr) * Name: stm32_seteprxaddr ****************************************************************************/ -static inline uint16 stm32_geteprxaddr(ubyte epno) +static inline uint16_t stm32_geteprxaddr(uint8_t epno) { - volatile uint32 *rxaddr = (uint32*)STM32_USB_ADDR_RX(epno); - return (uint16)*rxaddr; + volatile uint32_t *rxaddr = (uint32_t*)STM32_USB_ADDR_RX(epno); + return (uint16_t)*rxaddr; } /**************************************************************************** * Name: stm32_setepaddress ****************************************************************************/ -static inline void stm32_setepaddress(ubyte epno, uint16 addr) +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; @@ -789,10 +791,10 @@ static inline void stm32_setepaddress(ubyte epno, uint16 addr) * Name: stm32_seteptype ****************************************************************************/ -static inline void stm32_seteptype(ubyte epno, uint16 type) +static inline void stm32_seteptype(uint8_t epno, uint16_t type) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; @@ -805,10 +807,10 @@ static inline void stm32_seteptype(ubyte epno, uint16 type) * Name: stm32_setstatusout ****************************************************************************/ -static inline void stm32_setstatusout(ubyte epno) +static inline void stm32_setstatusout(uint8_t epno) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; * for a CONTROL endpoint, it is set to indicate that a status OUT @@ -825,10 +827,10 @@ static inline void stm32_setstatusout(ubyte epno) * Name: stm32_clrstatusout ****************************************************************************/ -static inline void stm32_clrstatusout(ubyte epno) +static inline void stm32_clrstatusout(uint8_t epno) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; * for a CONTROL endpoint, it is set to indicate that a status OUT @@ -845,10 +847,10 @@ static inline void stm32_clrstatusout(ubyte epno) * Name: stm32_clrrxdtog ****************************************************************************/ -static void stm32_clrrxdtog(ubyte epno) +static void stm32_clrrxdtog(uint8_t epno) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_RX) != 0) @@ -863,10 +865,10 @@ static void stm32_clrrxdtog(ubyte epno) * Name: stm32_clrtxdtog ****************************************************************************/ -static void stm32_clrtxdtog(ubyte epno) +static void stm32_clrtxdtog(uint8_t epno) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_TX) != 0) @@ -881,10 +883,10 @@ static void stm32_clrtxdtog(ubyte epno) * Name: stm32_clrepctrrx ****************************************************************************/ -static void stm32_clrepctrrx(ubyte epno) +static void stm32_clrepctrrx(uint8_t epno) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; @@ -896,10 +898,10 @@ static void stm32_clrepctrrx(ubyte epno) * Name: stm32_clrepctrtx ****************************************************************************/ -static void stm32_clrepctrtx(ubyte epno) +static void stm32_clrepctrtx(uint8_t epno) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; @@ -911,16 +913,16 @@ static void stm32_clrepctrtx(ubyte epno) * Name: stm32_geteptxstatus ****************************************************************************/ -static inline uint16 stm32_geteptxstatus(ubyte epno) +static inline uint16_t stm32_geteptxstatus(uint8_t epno) { - return (uint16)(stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATTX_MASK); + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATTX_MASK); } /**************************************************************************** * Name: stm32_geteprxstatus ****************************************************************************/ -static inline uint16 stm32_geteprxstatus(ubyte epno) +static inline uint16_t stm32_geteprxstatus(uint8_t epno) { return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); } @@ -929,10 +931,10 @@ static inline uint16 stm32_geteprxstatus(ubyte epno) * Name: stm32_seteptxstatus ****************************************************************************/ -static void stm32_seteptxstatus(ubyte epno, uint16 state) +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr) & EPR_TXDTOG_MASK; @@ -957,10 +959,10 @@ static void stm32_seteptxstatus(ubyte epno, uint16 state) * Name: stm32_seteprxstatus ****************************************************************************/ -static void stm32_seteprxstatus(ubyte epno, uint16 state) +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) { - uint32 epaddr = STM32_USB_EPR(epno); - uint16 regval; + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; regval = stm32_getreg(epaddr) & EPR_RXDTOG_MASK; @@ -985,7 +987,7 @@ static void stm32_seteprxstatus(ubyte epno, uint16 state) * Name: stm32_eptxstalled ****************************************************************************/ -static inline uint16 stm32_eptxstalled(ubyte epno) +static inline uint16_t stm32_eptxstalled(uint8_t epno) { return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); } @@ -994,7 +996,7 @@ static inline uint16 stm32_eptxstalled(ubyte epno) * Name: stm32_eprxstalled ****************************************************************************/ -static inline uint16 stm32_eprxstalled(ubyte epno) +static inline uint16_t stm32_eprxstalled(uint8_t epno) { return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); } @@ -1006,27 +1008,27 @@ static inline uint16 stm32_eprxstalled(ubyte epno) * Name: stm32_copytopma ****************************************************************************/ -static void stm32_copytopma(const ubyte *buffer, uint16 pma, uint16 nbytes) +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes) { - uint16 *dest; - uint16 ms; - uint16 ls; + uint16_t *dest; + uint16_t ms; + uint16_t ls; int nwords = (nbytes + 1) >> 1; int i; /* Copy loop. Source=user buffer, Dest=packet memory */ - dest = (uint16*)(STM32_USBCANRAM_BASE + ((uint32)pma << 1)); + dest = (uint16_t*)(STM32_USBCANRAM_BASE + ((uint32_t)pma << 1)); for (i = nwords; i != 0; i--) { /* Read two bytes and pack into on 16-bit word */ - ls = (uint16)(*buffer++); - ms = (uint16)(*buffer++); + ls = (uint16_t)(*buffer++); + ms = (uint16_t)(*buffer++); *dest = ms << 8 | ls; - /* Source address increments by 2*sizeof(ubyte) = 2; Dest address - * increments by 2*sizeof(uint16) = 4. + /* Source address increments by 2*sizeof(uint8_t) = 2; Dest address + * increments by 2*sizeof(uint16_t) = 4. */ dest += 2; @@ -1038,23 +1040,23 @@ static void stm32_copytopma(const ubyte *buffer, uint16 pma, uint16 nbytes) ****************************************************************************/ static inline void -stm32_copyfrompma(ubyte *buffer, uint16 pma, uint16 nbytes) +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) { - uint32 *src; + uint32_t *src; int nwords = (nbytes + 1) >> 1; int i; /* Copy loop. Source=packet memory, Dest=user buffer */ - src = (uint32*)(STM32_USBCANRAM_BASE + ((uint32)pma << 1)); + src = (uint32_t*)(STM32_USBCANRAM_BASE + ((uint32_t)pma << 1)); for (i = nwords; i != 0; i--) { /* Copy 16-bits from packet memory to user buffer. */ - *(uint16*)buffer = *src++; + *(uint16_t*)buffer = *src++; - /* Source address increments by 1*sizeof(uint32) = 4; Dest address - * increments by 2*sizeof(ubyte) = 2. + /* Source address increments by 1*sizeof(uint32_t) = 4; Dest address + * increments by 2*sizeof(uint8_t) = 2. */ buffer += 2; @@ -1108,9 +1110,9 @@ static void stm32_rqenqueue(struct stm32_ep_s *privep, ****************************************************************************/ static inline void -stm32_abortrequest(struct stm32_ep_s *privep, struct stm32_req_s *privreq, sint16 result) +stm32_abortrequest(struct stm32_ep_s *privep, struct stm32_req_s *privreq, int16_t result) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), (uint16)USB_EPNO(privep->ep.eplog)); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), (uint16_t)USB_EPNO(privep->ep.eplog)); /* Save the result in the request structure */ @@ -1125,7 +1127,7 @@ stm32_abortrequest(struct stm32_ep_s *privep, struct stm32_req_s *privreq, sint1 * Name: stm32_reqcomplete ****************************************************************************/ -static void stm32_reqcomplete(struct stm32_ep_s *privep, sint16 result) +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) { struct stm32_req_s *privreq; irqstate_t flags; @@ -1142,7 +1144,7 @@ static void stm32_reqcomplete(struct stm32_ep_s *privep, sint16 result) * in the callback. */ - boolean stalled = privep->stalled; + bool stalled = privep->stalled; if (USB_EPNO(privep->ep.eplog) == EP0) { privep->stalled = (privep->dev->devstate == DEVSTATE_STALLED); @@ -1169,9 +1171,9 @@ static void stm32_reqcomplete(struct stm32_ep_s *privep, sint16 result) static void stm32_epwrite(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep, - const ubyte *buf, uint32 nbytes) + const uint8_t *buf, uint32_t nbytes) { - ubyte epno = USB_EPNO(privep->ep.eplog); + uint8_t epno = USB_EPNO(privep->ep.eplog); usbtrace(TRACE_WRITE(epno), nbytes); /* Check for a zero-length packet */ @@ -1194,7 +1196,7 @@ static void stm32_epwrite(struct stm32_usbdev_s *priv, * when the next data out interrupt is received. */ - privep->txbusy = TRUE; + privep->txbusy = true; } /**************************************************************************** @@ -1204,8 +1206,8 @@ static void stm32_epwrite(struct stm32_usbdev_s *priv, static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { struct stm32_req_s *privreq; - ubyte *buf; - ubyte epno; + uint8_t *buf; + uint8_t epno; int nbytes; int bytesleft; @@ -1213,7 +1215,7 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive * there is no TX transfer in progress. */ - privep->txbusy = FALSE; + privep->txbusy = false; /* Check the request from the head of the endpoint request queue */ @@ -1299,9 +1301,9 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive static int stm32_rdrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { struct stm32_req_s *privreq; - uint32 src; - ubyte *dest; - ubyte epno; + uint32_t src; + uint8_t *dest; + uint8_t epno; int pmalen; int readlen; @@ -1333,7 +1335,7 @@ static int stm32_rdrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); - /* Get the source and desintion transfer addresses */ + /* Get the source and destination transfer addresses */ dest = privreq->req.buf + privreq->req.xfrd; src = stm32_geteprxaddr(epno); @@ -1412,10 +1414,10 @@ static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) * Name: stm32_epdone ****************************************************************************/ -static void stm32_epdone(struct stm32_usbdev_s *priv, ubyte epno) +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) { struct stm32_ep_s *privep; - uint16 epr; + uint16_t epr; /* Decode and service non control endpoints interrupt */ @@ -1444,14 +1446,14 @@ static void stm32_epdone(struct stm32_usbdev_s *priv, ubyte epno) } else { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16)epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); /* Mark the RX processing as pending and NAK any OUT actions * on this endpoint */ priv->rxstatus = USB_EPR_STATRX_NAK; - priv->rxpending = TRUE; + priv->rxpending = true; } /* Clear the interrupt status and set the new RX status */ @@ -1486,7 +1488,7 @@ static void stm32_epdone(struct stm32_usbdev_s *priv, ubyte epno) * Name: stm32_setdevaddr ****************************************************************************/ -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, ubyte value) +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) { int epno; @@ -1496,7 +1498,7 @@ static void stm32_setdevaddr(struct stm32_usbdev_s *priv, ubyte value) { if (stm32_epreserved(priv, epno)) { - stm32_setepaddress((ubyte)epno, (ubyte)epno); + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); } } @@ -1518,8 +1520,8 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) union wb_u index; union wb_u len; union wb_u response; - boolean handled = FALSE; - ubyte epno; + bool handled = false; + uint8_t epno; int nbytes = 0; /* Assume zero-length packet */ int ret; @@ -1529,7 +1531,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) while (!stm32_rqempty(ep0)) { - sint16 result = OK; + int16_t result = OK; if (privreq->req.xfrd != privreq->req.len) { result = -EPROTO; @@ -1546,7 +1548,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) /* Get a 32-bit PMA address and use that to get the 8-byte setup request */ - stm32_copyfrompma((ubyte*)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ); + stm32_copyfrompma((uint8_t*)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ); /* And extract the little-endian 16-bit values to host order */ @@ -1693,7 +1695,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) */ stm32_dispatchrequest(priv); - handled = TRUE; + handled = true; } else { @@ -1705,7 +1707,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) { privep = &priv->eplist[epno]; privep->halted = 0; - ret = stm32_epstall(&privep->ep, TRUE); + ret = stm32_epstall(&privep->ep, true); } else { @@ -1737,7 +1739,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) /* The class driver handles all recipients except recipient=endpoint */ stm32_dispatchrequest(priv); - handled = TRUE; + handled = true; } else { @@ -1749,7 +1751,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) { privep = &priv->eplist[epno]; privep->halted = 1; - ret = stm32_epstall(&privep->ep, FALSE); + ret = stm32_epstall(&privep->ep, false); } else { @@ -1803,7 +1805,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) /* The request seems valid... let the class implementation handle it */ stm32_dispatchrequest(priv); - handled = TRUE; + handled = true; } else { @@ -1828,7 +1830,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) /* The request seems valid... let the class implementation handle it */ stm32_dispatchrequest(priv); - handled = TRUE; + handled = true; } else { @@ -1853,7 +1855,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) /* The request seems valid... let the class implementation handle it */ stm32_dispatchrequest(priv); - handled = TRUE; + handled = true; } else { @@ -1881,7 +1883,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); stm32_dispatchrequest(priv); - handled = TRUE; + handled = true; } break; @@ -1912,7 +1914,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv) * must be sent (may be a zero length packet). * 2. The request was successfully handled by the class implementation. In * case, the EP0 IN response has already been queued and the local variable - * 'handled' will be set to TRUE and devstate != DEVSTATE_STALLED; + * 'handled' will be set to true and devstate != DEVSTATE_STALLED; * 3. An error was detected in either the above logic or by the class implementation * logic. In either case, priv->state will be set DEVSTATE_STALLED * to indicate this case. @@ -1948,7 +1950,7 @@ static void stm32_ep0in(struct stm32_usbdev_s *priv) { /* There is no longer anything in the EP0 TX packet memory */ - priv->eplist[EP0].txbusy = FALSE; + priv->eplist[EP0].txbusy = false; /* Are we processing the completion of one packet of an outgoing request * from the class driver? @@ -2009,9 +2011,9 @@ static void stm32_ep0out(struct stm32_usbdev_s *priv) * Name: stm32_ep0done ****************************************************************************/ -static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16 istr) +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) { - uint16 epr; + uint16_t epr; /* Initialize RX and TX status. We shouldn't have to actually look at the * status because the hardware is supposed to set the both RX and TX status @@ -2134,18 +2136,18 @@ static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16 istr) static void stm32_lptransfer(struct stm32_usbdev_s *priv) { - ubyte epno; - uint16 istr; + uint8_t epno; + uint16_t istr; /* Stay in loop while LP interrupts are pending */ while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32_putreg((uint16)~USB_ISTR_CTR, STM32_USB_ISTR); + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ - epno = (ubyte)(istr & USB_ISTR_EPID_MASK); + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); /* Handle EP0 completion events */ @@ -2175,8 +2177,8 @@ static int stm32_hpinterrupt(int irq, void *context) */ struct stm32_usbdev_s *priv = &g_usbdev; - uint16 istr; - ubyte epno; + uint16_t istr; + uint8_t epno; /* High priority interrupts are only triggered by a correct transfer event * for isochronous and double-buffer bulk transfers. @@ -2186,11 +2188,11 @@ static int stm32_hpinterrupt(int irq, void *context) usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_HPINTERRUPT), istr); while ((istr & USB_ISTR_CTR) != 0) { - stm32_putreg((uint16)~USB_ISTR_CTR, STM32_USB_ISTR); + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ - epno = (ubyte)(istr & USB_ISTR_EPID_MASK); + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); /* And handle the completion event */ @@ -2217,7 +2219,7 @@ static int stm32_lpinterrupt(int irq, void *context) */ struct stm32_usbdev_s *priv = &g_usbdev; - uint16 istr = stm32_getreg(STM32_USB_ISTR); + uint16_t istr = stm32_getreg(STM32_USB_ISTR); usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_LPINTERRUPT), istr); @@ -2306,9 +2308,9 @@ exit_lpinterrupt: ****************************************************************************/ static void -stm32_setimask(struct stm32_usbdev_s *priv, uint16 setbits, uint16 clrbits) +stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits) { - uint16 regval; + uint16_t regval; /* Adjust the interrupt mask bits in the shadow copy first */ @@ -2334,7 +2336,7 @@ stm32_setimask(struct stm32_usbdev_s *priv, uint16 setbits, uint16 clrbits) static void stm32_suspend(struct stm32_usbdev_s *priv) { - uint16 regval; + uint16_t regval; /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP * interrupt. Clear any pending WKUP interrupt. @@ -2369,7 +2371,7 @@ static void stm32_suspend(struct stm32_usbdev_s *priv) * state */ - stm32_usbsuspend((struct usbdev_s *)priv, FALSE); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** @@ -2378,7 +2380,7 @@ static void stm32_suspend(struct stm32_usbdev_s *priv) static void stm32_initresume(struct stm32_usbdev_s *priv) { - uint16 regval; + uint16_t regval; /* This function is called when either (1) a WKUP interrupt is received from * the host PC, or (2) the class device implementation calls the wakeup() @@ -2396,7 +2398,7 @@ static void stm32_initresume(struct stm32_usbdev_s *priv) /* Restore full power -- whatever that means for this particular board */ - stm32_usbsuspend((struct usbdev_s *)priv, TRUE); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Reset FSUSP bit and enable normal interrupt handling */ @@ -2409,7 +2411,7 @@ static void stm32_initresume(struct stm32_usbdev_s *priv) static void stm32_esofpoll(struct stm32_usbdev_s *priv) { - uint16 regval; + uint16_t regval; /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */ @@ -2462,7 +2464,7 @@ static void stm32_esofpoll(struct stm32_usbdev_s *priv) ****************************************************************************/ static inline struct stm32_ep_s * -stm32_epreserve(struct stm32_usbdev_s *priv, ubyte epset) +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) { struct stm32_ep_s *privep = NULL; irqstate_t flags; @@ -2478,7 +2480,7 @@ stm32_epreserve(struct stm32_usbdev_s *priv, ubyte epset) for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) { - ubyte bit = STM32_ENDP_BIT(epndx); + uint8_t bit = STM32_ENDP_BIT(epndx); if ((epset & bit) != 0) { /* Mark the endpoint no longer available */ @@ -2513,7 +2515,7 @@ stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) * Name: stm32_epreserved ****************************************************************************/ -static inline boolean +static inline bool stm32_epreserved(struct stm32_usbdev_s *priv, int epno) { return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); @@ -2534,7 +2536,7 @@ static int stm32_epallocpma(struct stm32_usbdev_s *priv) { /* Check if this buffer is available */ - ubyte bit = STM32_BUFFER_BIT(bufndx); + uint8_t bit = STM32_BUFFER_BIT(bufndx); if ((priv->bufavail & bit) != 0) { /* Yes.. Mark the endpoint no longer available */ @@ -2573,13 +2575,13 @@ stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, - boolean last) + bool last) { struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - uint16 pma; - uint16 setting; - uint16 maxpacket; - ubyte epno; + uint16_t pma; + uint16_t setting; + uint16_t maxpacket; + uint8_t epno; #ifdef CONFIG_DEBUG if (!ep || !desc) @@ -2593,7 +2595,7 @@ static int stm32_epconfigure(struct usbdev_ep_s *ep, /* Get the unadorned endpoint address */ epno = USB_EPNO(desc->addr); - usbtrace(TRACE_EPCONFIGURE, (uint16)epno); + usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); DEBUGASSERT(epno == USB_EPNO(ep->eplog)); /* Set the requested type */ @@ -2618,7 +2620,7 @@ static int stm32_epconfigure(struct usbdev_ep_s *ep, break; default: - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16)desc->type); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16_t)desc->type); return -EINVAL; } @@ -2675,7 +2677,7 @@ static int stm32_epdisable(struct usbdev_ep_s *ep) { struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; - ubyte epno; + uint8_t epno; #ifdef CONFIG_DEBUG if (!ep) @@ -2762,7 +2764,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; struct stm32_usbdev_s *priv; irqstate_t flags; - ubyte epno; + uint8_t epno; int ret = OK; #ifdef CONFIG_DEBUG @@ -2847,7 +2849,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) /* Clear the pending interrupt status */ stm32_clrepctrrx(epno); - priv->rxpending = FALSE; + priv->rxpending = false; /* Set the new RX status */ @@ -2889,12 +2891,12 @@ static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) * Name: stm32_epstall ****************************************************************************/ -static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume) +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) { struct stm32_ep_s *privep; struct stm32_usbdev_s *priv; - ubyte epno = USB_EPNO(ep->eplog); - uint16 status; + uint8_t epno = USB_EPNO(ep->eplog); + uint16_t status; irqstate_t flags; #ifdef CONFIG_DEBUG @@ -2940,7 +2942,7 @@ static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume) /* Resuming a stalled endpoint */ usbtrace(TRACE_EPRESUME, epno); - privep->stalled = FALSE; + privep->stalled = false; if (USB_ISEPIN(ep->eplog)) { @@ -2988,7 +2990,7 @@ static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume) else { usbtrace(TRACE_EPSTALL, epno); - privep->stalled = TRUE; + privep->stalled = true; if (USB_ISEPIN(ep->eplog)) { @@ -3017,15 +3019,15 @@ static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume) * Name: stm32_allocep ****************************************************************************/ -static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, ubyte epno, - boolean in, ubyte eptype) +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, + bool in, uint8_t eptype) { struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; struct stm32_ep_s *privep = NULL; - ubyte epset = STM32_ENDP_ALLSET; + uint8_t epset = STM32_ENDP_ALLSET; int bufno; - usbtrace(TRACE_DEVALLOCEP, (uint16)epno); + usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); #ifdef CONFIG_DEBUG if (!dev) { @@ -3051,7 +3053,7 @@ static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, ubyte epno, if (epno >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16)epno); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); return NULL; } @@ -3068,7 +3070,7 @@ static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, ubyte epno, privep = stm32_epreserve(priv, epset); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16)epset); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); goto errout; } epno = USB_EPNO(privep->ep.eplog); @@ -3082,7 +3084,7 @@ static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, ubyte epno, usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); goto errout_with_ep; } - privep->bufno = (ubyte)bufno; + privep->bufno = (uint8_t)bufno; return &privep->ep; errout_with_ep: @@ -3109,7 +3111,7 @@ static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) #endif priv = (struct stm32_usbdev_s *)dev; privep = (struct stm32_ep_s *)ep; - usbtrace(TRACE_DEVFREEEP, (uint16)USB_EPNO(ep->eplog)); + usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); if (priv && privep) { @@ -3129,7 +3131,7 @@ static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) static int stm32_getframe(struct usbdev_s *dev) { - uint16 fnr; + uint16_t fnr; #ifdef CONFIG_DEBUG if (!dev) @@ -3188,11 +3190,11 @@ static int stm32_wakeup(struct usbdev_s *dev) * Name: stm32_selfpowered ****************************************************************************/ -static int stm32_selfpowered(struct usbdev_s *dev, boolean selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - usbtrace(TRACE_DEVSELFPOWERED, (uint16)selfpowered); + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); #ifdef CONFIG_DEBUG if (!dev) @@ -3232,7 +3234,7 @@ static void stm32_reset(struct stm32_usbdev_s *priv) priv->devstate = DEVSTATE_IDLE; priv->rsmstate = RSMSTATE_IDLE; - priv->rxpending = FALSE; + priv->rxpending = false; /* Reset endpoints */ @@ -3252,10 +3254,10 @@ static void stm32_reset(struct stm32_usbdev_s *priv) /* Reset endpoint status */ - privep->stalled = FALSE; - privep->halted = FALSE; - privep->txbusy = FALSE; - privep->txnullpkt = FALSE; + privep->stalled = false; + privep->halted = false; + privep->txbusy = false; + privep->txnullpkt = false; } /* Re-configure the USB controller in its initial, unconnected state */ @@ -3345,7 +3347,7 @@ void up_usbinitialize(void) * host to enumerate us until the class driver is registered. */ - stm32_usbpullup(&priv->usbdev, FALSE); + stm32_usbpullup(&priv->usbdev, false); /* Initialize the device state structure. NOTE: many fields * have the initial value of zero and, hence, are not explicitly @@ -3416,14 +3418,14 @@ void up_usbinitialize(void) if (irq_attach(STM32_IRQ_USBHPCANTX, stm32_hpinterrupt) != 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), - (uint16)STM32_IRQ_USBHPCANTX); + (uint16_t)STM32_IRQ_USBHPCANTX); goto errout; } if (irq_attach(STM32_IRQ_USBLPCANRX0, stm32_lpinterrupt) != 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), - (uint16)STM32_IRQ_USBLPCANRX0); + (uint16_t)STM32_IRQ_USBLPCANRX0); goto errout; } return; @@ -3452,7 +3454,7 @@ void up_usbuninitialize(void) */ struct stm32_usbdev_s *priv = &g_usbdev; - uint16 regval; + uint16_t regval; irqstate_t flags; usbtrace(TRACE_DEVUNINIT, 0); @@ -3483,7 +3485,7 @@ void up_usbuninitialize(void) /* Disconnect the device / disable the pull-up */ - stm32_usbpullup(&priv->usbdev, FALSE); + stm32_usbpullup(&priv->usbdev, false); /* Power down the USB controller */ @@ -3536,7 +3538,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); priv->driver = NULL; } else @@ -3559,7 +3561,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * some time after this */ - stm32_usbpullup(&priv->usbdev, TRUE); + stm32_usbpullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } return ret; diff --git a/nuttx/arch/arm/src/stm32/stm32_usbdev.h b/nuttx/arch/arm/src/stm32/stm32_usbdev.h index 2774e49c8..ae2df5dc1 100644 --- a/nuttx/arch/arm/src/stm32/stm32_usbdev.h +++ b/nuttx/arch/arm/src/stm32/stm32_usbdev.h @@ -41,7 +41,7 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> +#include <stdint.h> #include "chip.h" /************************************************************************************ @@ -77,7 +77,7 @@ #define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ #define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ -#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) +#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) #define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) #define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) #define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) diff --git a/nuttx/arch/arm/src/stm32/stm32_wdg.h b/nuttx/arch/arm/src/stm32/stm32_wdg.h index 0e574e3be..d5a1ee2df 100644 --- a/nuttx/arch/arm/src/stm32/stm32_wdg.h +++ b/nuttx/arch/arm/src/stm32/stm32_wdg.h @@ -41,11 +41,11 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> + #include "chip.h" /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Register Offsets *****************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h b/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h index c2b8473f4..93f7e9d84 100644 --- a/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h +++ b/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h @@ -41,10 +41,9 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <sys/types.h> /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Alternate Pin Functions: */ diff --git a/nuttx/arch/arm/src/stm32/stm32f107vc_pinmap.h b/nuttx/arch/arm/src/stm32/stm32f107vc_pinmap.h index a35ff741f..1e81e1434 100755 --- a/nuttx/arch/arm/src/stm32/stm32f107vc_pinmap.h +++ b/nuttx/arch/arm/src/stm32/stm32f107vc_pinmap.h @@ -41,10 +41,9 @@ ************************************************************************************/
#include <nuttx/config.h>
-#include <sys/types.h>
/************************************************************************************
- * Definitions
+ * Pre-processor Definitions
************************************************************************************/
/* Alternate Pin Functions: */
|