Incoporate new ARMv7-M exception handling logic contributed by Mike Smith

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4413 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 119 insertions, 10 deletions

diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs
index 213ac0be9..351680685 100644
--- a/nuttx/arch/arm/src/stm32/Make.defs
+++ b/nuttx/arch/arm/src/stm32/Make.defs
@@ -33,7 +33,11 @@
 #
 ############################################################################
 
+ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
+HEAD_ASRC	= 
+else
 HEAD_ASRC	= stm32_vectors.S
+endif
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c \
@@ -44,6 +48,11 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c \
 		  up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
 		  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
 
+ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
+CMN_ASRCS	+= up_exception.S stm32_vectors.S
+CMN_CSRCS	+= up_vectors.c
+endif
+
 ifeq ($(CONFIG_DEBUG_STACK),y)
 CMN_CSRCS	+= up_checkstack.c
 endif
@@ -59,6 +68,10 @@ CHIP_CSRCS	= stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c \
 		  stm32_spi.c stm32_usbdev.c stm32_sdio.c stm32_tim.c stm32_i2c.c \
 		  stm32_waste.c
 
+ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
+CHIP_ASRCS	+= stm32_vectors.S
+endif
+
 ifneq ($(CONFIG_IDLE_CUSTOM),y)
 CHIP_CSRCS	+= stm32_idle.c
 endif
diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h
index 5a560edfe..3bceac77b 100644
--- a/nuttx/arch/arm/src/stm32/chip.h
+++ b/nuttx/arch/arm/src/stm32/chip.h
@@ -49,7 +49,7 @@
 /* Include the chip pin configuration file */
 
 #if defined(CONFIG_STM32_STM32F10XX)
-#  if defined(CONFIG_ARCH_CHIP_STM32F103ZET6) 
+#  if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
 #    include "chip/stm32f103ze_pinmap.h"
 #  elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
 #    include "chip/stm32f103re_pinmap.h"
@@ -63,7 +63,21 @@
 #elif defined(CONFIG_STM32_STM32F40XX)
 #  include "chip/stm32f40xxx_pinmap.h"
 #else
-#  error "Unsupported STM32 chip"
+#  error "No pinmap file for this STM32 chip"
+#endif
+
+/* If the common ARMv7-M vector handling logic is used, then include the
+ * required vector definitions as well.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+#  if defined(CONFIG_STM32_STM32F10XX)
+#    include "chip/stm32f10xxx_vectors.h"
+#  elif defined(CONFIG_STM32_STM32F40XX)
+#    include "chip/stm32f40xxx_vectors.h"
+#  else
+#    error "No vector file for this STM32 family"
+#  endif
 #endif
 
 /* Include only the mchip emory map. */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
index 0d6b965d2..8ce98c988 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
@@ -36,7 +36,6 @@
 /************************************************************************************
  * Pre-processor definitions
  ************************************************************************************/
-
 /* This file is included by stm32_vectors.S.  It provides the macro VECTOR that
  * supplies ach STM32F10xxx vector in terms of a (lower-case) ISR label and an
  * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f10xxx_irq.h.
@@ -46,6 +45,18 @@
 
 #ifdef CONFIG_STM32_CONNECTIVITY_LINE
 
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 68 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 68
+
+#else
+
 VECTOR(stm32_wwdg, STM32_IRQ_WWDG)               /* Vector 16+0:  Window Watchdog interrupt */
 VECTOR(stm32_pvd, STM32_IRQ_PVD)                 /* Vector 16+1:  PVD through EXTI Line detection interrupt */
 VECTOR(stm32_tamper, STM32_IRQ_TAMPER)           /* Vector 16+2:  Tamper interrupt */
@@ -107,6 +118,19 @@ VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1)         /* Vector 16+65: CAN2 RX1 inter
 VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE)         /* Vector 16+66: CAN2 SCE interrupt */
 VECTOR(stm32_otgfs, STM32_IRQ_OTGFS)             /* Vector 16+67: USB On The Go FS global interrupt */
 
+#endif /* CONFIG_ARMV7M_CMNVECTOR */
+#else /* CONFIG_STM32_CONNECTIVITY_LINE */
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 60 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 60
+
 #else
 
 VECTOR(stm32_wwdg, STM32_IRQ_WWDG)               /* Vector 16+0:  Window Watchdog interrupt */
@@ -169,4 +193,6 @@ VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1)         /* Vector 16+56: DMA2 Channel 1
 VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2)         /* Vector 16+57: DMA2 Channel 2 global interrupt */
 VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3)         /* Vector 16+58: DMA2 Channel 3 global interrupt */
 VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45)       /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
-#endif
+
+#endif /* CONFIG_ARMV7M_CMNVECTOR */
+#endif /* CONFIG_STM32_CONNECTIVITY_LINE */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
index 2bc949fec..0965a7224 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
  *
- *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -44,6 +44,18 @@
  * the interrupt vectors and handlers in their final form.
  */
 
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 84 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 82
+
+#else
+
 VECTOR(stm32_wwdg, STM32_IRQ_WWDG)               /* Vector 16+0:  Window Watchdog interrupt */
 VECTOR(stm32_pvd, STM32_IRQ_PVD)                 /* Vector 16+1:  PVD through EXTI Line detection interrupt */
 VECTOR(stm32_tamper, STM32_IRQ_TAMPER)           /* Vector 16+2:  Tamper and time stamp interrupts */
@@ -127,3 +139,4 @@ VECTOR(stm32_cryp, STM32_IRQ_CRYP)               /* Vector 16+79: CRYP crypto gl
 VECTOR(stm32_hash, STM32_IRQ_HASH)               /* Vector 16+80: Hash and Rng global interrupt */
 VECTOR(stm32_fpu, STM32_IRQ_FPU)                 /* Vector 16+81: FPU global interrupt */
 
+#endif /* CONFIG_ARMV7M_CMNVECTOR */
diff --git a/nuttx/arch/arm/src/stm32/stm32_start.c b/nuttx/arch/arm/src/stm32/stm32_start.c
index b1b2af297..5f4a4c9c9 100644
--- a/nuttx/arch/arm/src/stm32/stm32_start.c
+++ b/nuttx/arch/arm/src/stm32/stm32_start.c
@@ -71,22 +71,55 @@
  * Public Functions
  ****************************************************************************/
 
- /****************************************************************************
+/****************************************************************************
  * Name: stm32_fpuconfig
  *
  * Description:
- *   Configure the FPU.  The the MCU has an FPU, then enable full access
- *   to coprocessors CP10 and CP11.
+ *   Configure the FPU.
+ *
+ *   1. The MCU has an FPU, then enable full access to coprocessors CP10 and
+ *      CP11.
+ *
+ *   if the common ARMv-7M interrupt vector handling is used (via
+ *   CONFIG_ARMV7M_CMNVECTOR=y), then lazy floating point register saving is
+ *   disabled and this function will also:
+ *
+ *   2. Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+ *     with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
+ *     are going to turn on CONTROL.FPCA for all contexts.
+ *
+ *   3. Set CONTROL.FPCA so that we always get the extended context frame
+ *      with the volatile FP registers stacked above the basic context.
  *
  ****************************************************************************/
 
 #ifdef CONFIG_ARCH_FPU
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+#  define stm32_fpuconfig() \
+{ \
+  uint32_t regval;\
+  regval = getcontrol(); \
+  regval |= 1<<2; \
+  setcontrol(regval); \
+  regval = getreg32(NVIC_FPCCR); \
+  regval &= ~((1 << 31) | (1 << 30)); \
+  putreg32(regval, NVIC_FPCCR); \
+  regval = getreg32(NVIC_CPACR); \
+  regval |= ((3 << (2*10)) | (3 << (2*11))); \
+  putreg32(regval, NVIC_CPACR); \
+}
+
+#else
+
 #  define stm32_fpuconfig() \
 { \
   uint32_t regval = getreg32(NVIC_CPACR); \
   regval |= ((3 << (2*10)) | (3 << (2*11))); \
   putreg32(regval, NVIC_CPACR); \
 }
+#endif
+
 #else
 #  define stm32_fpuconfig()
 #endif
diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S
index ee4220ccc..91f530f05 100644
--- a/nuttx/arch/arm/src/stm32/stm32_vectors.S
+++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S
@@ -2,7 +2,7 @@
  * arch/arm/src/stm32/stm32_vectors.S
  * arch/arm/src/chip/stm32_vectors.S
  *
- *   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -40,14 +40,23 @@
 
 #include <nuttx/config.h>
 
+
 #include <arch/irq.h>
 
 #include "chip.h"
 
 /************************************************************************************
- * Preprocessor Definitions
+ * Configuration
  ************************************************************************************/
+/* Check if common ARMv7 interrupt vectoring is used (see
+ * arch/arm/src/armv7-m/up_vectors.S)
+ */
+
+#ifndef CONFIG_ARMV7M_CMNVECTOR
 
+/************************************************************************************
+ * Preprocessor Definitions
+ ************************************************************************************/
 /* Memory Map:
  *
  * 0x0800:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
@@ -334,6 +343,7 @@ up_interruptstack:
 g_intstackbase:
 	.size	up_interruptstack, .-up_interruptstack
 #endif
+#endif /* CONFIG_ARMV7M_CMNVECTOR */
 
 /************************************************************************************
  * .rodata