STM32 F4 RTC is functional

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4178 42af7a65-404d-4744-a932-0658087f49c3

2 files changed, 120 insertions, 4 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h
index c12698f7f..fdfa9b323 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h
@@ -55,6 +55,7 @@
 #define STM32_RTC_SSR_OFFSET      0x0028 /* RTC sub second register */
 #define STM32_RTC_SHIFTR_OFFSET   0x002c /* RTC shift control register */
 #define STM32_RTC_TSTR_OFFSET     0x0030 /* RTC time stamp time register */
+#define STM32_RTC_TSDR_OFFSET     0x0030 /* RTC time stamp date register */
 #define STM32_RTC_TSSSR_OFFSET    0x0038 /* RTC timestamp sub second register */
 #define STM32_RTC_CALR_OFFSET     0x003c /* RTC calibration register */
 #define STM32_RTC_TAFCR_OFFSET    0x0040 /* RTC tamper and alternate function configuration register */
@@ -98,6 +99,7 @@
 #define STM32_RTC_SSR             (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET)
 #define STM32_RTC_SHIFTR          (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET)
 #define STM32_RTC_TSTR            (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET)
+#define STM32_RTC_TSDR            (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET)
 #define STM32_RTC_TSSSR           (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET)
 #define STM32_RTC_CALR            (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET)
 #define STM32_RTC_TAFCR           (STM32_RTC_BASE+STM32_RTC_TAFCR_OFFSET)
@@ -151,7 +153,7 @@
 #define RTC_DR_DU_MASK            (15 << RTC_DR_DU_SHIFT)
 #define RTC_DR_DT_SHIFT           (4)       /* Bits 4-5: Date tens in BCD format */
 #define RTC_DR_DT_MASK            (3 << RTC_DR_DT_SHIFT)
-#define RTC_DR_MU_SHIFT           (20)      /* Bits 8-11: Month units in BCD format */
+#define RTC_DR_MU_SHIFT           (8)      /* Bits 8-11: Month units in BCD format */
 #define RTC_DR_MU_MASK            (15 << RTC_DR_MU_SHIFT)
 #define RTC_DR_MT                 (1 << 12) /* Bit 12: Month tens in BCD format */
 #define RTC_DR_WDU_SHIFT          (13)      /* Bits 13-15: Week day units */
@@ -298,6 +300,18 @@
 #define RTC_TSTR_HT_MASK          (3 << RTC_TSTR_HT_SHIFT)
 #define RTC_TSTR_PM               (1 << 22) /* Bit 22: AM/PM notation */
 
+/* RTC time stamp date register */
+
+#define RTC_TSDR_DU_SHIFT         (0)       /* Bit 0-3: Date units in BCD format */
+#define RTC_TSDR_DU_MASK          (15 << RTC_TSDR_DU_SHIFT) */
+#define RTC_TSDR_DT_SHIFT         (4)       /* Bits 4-5: Date tens in BCD format */
+#define RTC_TSDR_DT_MASK          (3 << RTC_TSDR_DT_SHIFT)
+#define RTC_TSDR_MU_SHIFT         (8)       /* Bits 8-11: Month units in BCD format */
+#define RTC_TSDR_MU_MASK          (xx << RTC_TSDR_MU_SHIFT)
+#define RTC_TSDR_MT               (1 << 12) /* Bit 12: Month tens in BCD format */
+#define RTC_TSDR_WDU_SHIFT        (13)      /* Bits 13-15: Week day units */
+#define RTC_TSDR_WDU_MASK         (7 << RTC_TSDR_WDU_SHIFT)
+
 /* RTC timestamp sub second register */
 
 #define RTC_TSSSR_MASK            (0xffff)  /* Bits 0-15: Sub second value */
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rtc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rtc.c
index 7eb1a896b..d2f2ab0b4 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rtc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rtc.c
@@ -45,6 +45,7 @@
 
 #include <time.h>
 #include <errno.h>
+#include <debug.h>
 
 #include <arch/board/board.h>
 
@@ -72,6 +73,10 @@
 #  error "CONFIG_STM32_PWR must selected to use this driver"
 #endif
 
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_DEBUG_RTC
+#endif
+
 /* Constants ************************************************************************/
 
 #define SYNCHRO_TIMEOUT  (0x00020000)
@@ -80,6 +85,20 @@
 #define RTC_PREDIV_S     (0xff)
 #define RTC_PREDIV_A     (0x7f)
 
+/* Debug ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_RTC
+#  define rtcdbg    dbg
+#  define rtcvdbg   vdbg
+#  define rtclldbg  lldbg
+#  define rtcllvdbg llvdbg
+#else
+#  define rtcdbg(x...)
+#  define rtcvdbg(x...)
+#  define rtclldbg(x...)
+#  define rtcllvdbg(x...)
+#endif
+
 /************************************************************************************
  * Private Types
  ************************************************************************************/
@@ -106,6 +125,76 @@ volatile bool g_rtc_enabled = false;
  * Private Functions
  ************************************************************************************/
 /************************************************************************************
+ * Name: rtc_dumpregs
+ *
+ * Description:
+ *    Disable RTC write protection
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_RTC
+static void rtc_dumpregs(FAR const char *msg)
+{
+  rtclldbg("%s:\n", msg);
+  rtclldbg("      TR: %08x\n", getreg32(STM32_RTC_TR));
+  rtclldbg("      DR: %08x\n", getreg32(STM32_RTC_DR));
+  rtclldbg("      CR: %08x\n", getreg32(STM32_RTC_CR));
+  rtclldbg("     ISR: %08x\n", getreg32(STM32_RTC_ISR));
+  rtclldbg("    PRER: %08x\n", getreg32(STM32_RTC_PRER));
+  rtclldbg("    WUTR: %08x\n", getreg32(STM32_RTC_WUTR));
+  rtclldbg("  CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR));
+  rtclldbg("  ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
+  rtclldbg("  ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR));
+  rtclldbg("  SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR));
+  rtclldbg("    TSTR: %08x\n", getreg32(STM32_RTC_TSTR));
+  rtclldbg("    TSDR: %08x\n", getreg32(STM32_RTC_TSDR));
+  rtclldbg("   TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR));
+  rtclldbg("    CALR: %08x\n", getreg32(STM32_RTC_CALR));
+  rtclldbg("   TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR));
+  rtclldbg("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
+  rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
+  rtclldbg("     BK0: %08x\n", getreg32(STM32_RTC_BK0R));
+}
+#else
+#  define tc_dumpregs(msg)
+#endif
+
+/************************************************************************************
+ * Name: rtc_dumptime
+ *
+ * Description:
+ *    Disable RTC write protection
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_RTC
+static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
+{
+  rtclldbg("%s:\n", msg);
+  rtclldbg("  tm_sec: %08x\n", tp->tm_sec);
+  rtclldbg("  tm_min: %08x\n", tp->tm_min);
+  rtclldbg(" tm_hour: %08x\n", tp->tm_hour);
+  rtclldbg(" tm_mday: %08x\n", tp->tm_mday);
+  rtclldbg("  tm_mon: %08x\n", tp->tm_mon);
+  rtclldbg(" tm_year: %08x\n", tp->tm_year);
+}
+#else
+#  define rtc_dumptime(tp, msg)
+#endif
+
+/************************************************************************************
  * Name: rtc_wprunlock
  *
  * Description:
@@ -485,6 +574,8 @@ int up_rtcinitialize(void)
   uint32_t regval;
   int ret;
 
+  rtc_dumpregs("On reset");
+
   /* Clocking for the PWR block must be provided.  However, this is done
    * unconditionally in stm32f40xxx_rcc.c on power up.  This done unconditionally
    * because the PWR block is also needed to set the internal voltage regulator for
@@ -508,6 +599,10 @@ int up_rtcinitialize(void)
       /* Perform the one-time setup of the LSE clocking to the RTC */
 
       ret = rtc_setup();
+
+      /* Remember that the RTC is initialized */
+
+      putreg32(RTC_MAGIC, STM32_RTC_BK0R);
     }
   else
     {
@@ -527,7 +622,7 @@ int up_rtcinitialize(void)
    */
 
 #ifdef CONFIG_RTC_ALARM
-#  warning "Missing logic"
+#  warning "Missing EXTI setup logic"
 
   /* Then attach the ALARM interrupt handler */
 
@@ -536,6 +631,7 @@ int up_rtcinitialize(void)
 #endif
 
   g_rtc_enabled = true;
+  rtc_dumpregs("After Initialzation");
   return OK;
 }
 
@@ -581,6 +677,8 @@ int up_rtc_getdatetime(FAR struct tm *tp)
     }
   while (tmp != dr);
 
+  rtc_dumpregs("Reading Time");
+
   /* Convert the RTC time to fields in struct tm format.  All of the STM32
    * All of the ranges of values correspond between struct tm and the time
    * register.
@@ -612,6 +710,8 @@ int up_rtc_getdatetime(FAR struct tm *tp)
 
   tmp = (dr & (RTC_DR_YU_MASK|RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT;
   tp->tm_year = rtc_bcd2bin(tmp) + 100;
+
+  rtc_dumptime(tp, "Returning");
   return OK;
 }
 
@@ -640,6 +740,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
   /* Break out the time values (not that the time is set only to units of seconds) */
 
   (void)gmtime_r(&tp->tv_sec, &newtime);
+  rtc_dumptime(&newtime, "Setting time");
 
   /* Then write the broken out values to the RTC */
 
@@ -663,8 +764,8 @@ int up_rtc_settime(FAR const struct timespec *tp)
    */
 
   dr = (rtc_bin2bcd(newtime.tm_mday) << RTC_DR_DU_SHIFT) |
-       ((rtc_bin2bcd(newtime.tm_mon) + 1)  << RTC_DR_MU_SHIFT) |
-       ((rtc_bin2bcd(newtime.tm_year) - 100) << RTC_DR_YU_SHIFT);
+       ((rtc_bin2bcd(newtime.tm_mon + 1))  << RTC_DR_MU_SHIFT) |
+       ((rtc_bin2bcd(newtime.tm_year - 100)) << RTC_DR_YU_SHIFT);
   dr &= ~RTC_DR_RESERVED_BITS;
 
   /* Disable the write protection for RTC registers */
@@ -692,6 +793,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
   /* Re-enable the write protection for RTC registers */
 
   rtc_wprlock();
+  rtc_dumpregs("New time setting");
   return ret;
 }