Add STM32L152X RCC PLL and FLASH support. Now compiles errorfree.

8 files changed, 664 insertions, 65 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
index aaa82727a..0f13b5a4e 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
@@ -40,21 +40,36 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-#if defined(CONFIG_STM32_LOWDENSITY)
+#if defined(CONFIG_STM32_STM32L15XX)
+/* The STM32 L15xx/L16xx can support up to 384KB of FLASH.  (In reality, supported
+ * L15xx parts have no more than 128KB). The program memory block is divided into
+ * 96 sectors of 4 Kbytes each, and each sector is further split up into 16 pages of
+ * 256 bytes each. The sector is the write protection granularity. In total, the
+ * program memory block contains 1536 pages.
+ */
+#  define STM32_FLASH_NPAGES        1536
+#  define STM32_FLASH_PAGESIZE      256
+
+#elif defined(CONFIG_STM32_LOWDENSITY)
 #  define STM32_FLASH_NPAGES        32
 #  define STM32_FLASH_PAGESIZE      1024
+
 #elif  defined(CONFIG_STM32_MEDIUMDENSITY)
 #  define STM32_FLASH_NPAGES        128
 #  define STM32_FLASH_PAGESIZE      1024
+
 #elif  defined(CONFIG_STM32_CONNECTIVITYLINE)
 #  define STM32_FLASH_NPAGES        128
 #  define STM32_FLASH_PAGESIZE      2048
+
 #elif defined(CONFIG_STM32_HIGHDENSITY)
 #  define STM32_FLASH_NPAGES        256
 #  define STM32_FLASH_PAGESIZE      2048
+
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  define STM32_FLASH_NPAGES        128
 #  define STM32_FLASH_PAGESIZE      (2*1024)
+
 #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #  define STM32_FLASH_NPAGES        8
 #  define STM32_FLASH_PAGESIZE      (128*1024)
@@ -78,6 +93,7 @@
 #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #  define STM32_FLASH_OPTCR_OFFSET 0x0014
 #endif
+
 #if defined(CONFIG_STM32_STM32F427)
 #  define STM32_FLASH_OPTCR1_OFFSET 0x0018
 #endif
@@ -104,30 +120,38 @@
 /* Register Bitfield Definitions ****************************************************/
 /* Flash Access Control Register (ACR) */
 
-#define FLASH_ACR_LATENCY_SHIFT     (0)
-#define FLASH_ACR_LATENCY_MASK      (7 << FLASH_ACR_LATENCY_SHIFT)
-#  define FLASH_ACR_LATENCY(n)      ((n) << FLASH_ACR_LATENCY_SHIFT)  /* n wait states */
-#  define FLASH_ACR_LATENCY_0       (0 << FLASH_ACR_LATENCY_SHIFT)    /* 000: Zero wait states */
-#  define FLASH_ACR_LATENCY_1       (1 << FLASH_ACR_LATENCY_SHIFT)    /* 001: One wait state */
-#  define FLASH_ACR_LATENCY_2       (2 << FLASH_ACR_LATENCY_SHIFT)    /* 010: Two wait states */
-#  define FLASH_ACR_LATENCY_3       (3 << FLASH_ACR_LATENCY_SHIFT)    /* 011: Three wait states */
-#  define FLASH_ACR_LATENCY_4       (4 << FLASH_ACR_LATENCY_SHIFT)    /* 100: Four wait states */
-#  define FLASH_ACR_LATENCY_5       (5 << FLASH_ACR_LATENCY_SHIFT)    /* 101: Five wait states */
-#  define FLASH_ACR_LATENCY_6       (6 << FLASH_ACR_LATENCY_SHIFT)    /* 110: Six wait states */
-#  define FLASH_ACR_LATENCY_7       (7 << FLASH_ACR_LATENCY_SHIFT)    /* 111: Seven wait states */
-
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
-#  define FLASH_ACR_HLFCYA          (1 << 3)  /* Bit 3: FLASH half cycle access */
-#  define FLASH_ACR_PRTFBE          (1 << 4)  /* Bit 4: FLASH prefetch enable */
-#  ifdef CONFIG_STM32_STM32F30XX
-#    define FLASH_ACR_PRFTBS        (1 << 5)  /* Bit 5: FLASH prefetch buffer status */
+#if defined(CONFIG_STM32_STM32L15XX)
+#  define FLASH_ACR_LATENCY         (1 << 0)  /* Bit 0: Latency */
+#  define FLASH_ACR_PRFTEN          (1 << 1)  /* Bit 1: Prefetch enable */
+#  define FLASH_ACR_ACC64           (1 << 2)  /* Bit 2: 64-bit access */
+#  define FLASH_ACR_SLEEP_PD        (1 << 3)  /* Bit 3: Flash mode during Sleep */
+#  define FLASH_ACR_RUN_PD          (1 << 4)  /* Bit 4: Flash mode during Run */
+#else
+#  define FLASH_ACR_LATENCY_SHIFT   (0)
+#  define FLASH_ACR_LATENCY_MASK    (7 << FLASH_ACR_LATENCY_SHIFT)
+#    define FLASH_ACR_LATENCY(n)    ((n) << FLASH_ACR_LATENCY_SHIFT)  /* n wait states */
+#    define FLASH_ACR_LATENCY_0     (0 << FLASH_ACR_LATENCY_SHIFT)    /* 000: Zero wait states */
+#    define FLASH_ACR_LATENCY_1     (1 << FLASH_ACR_LATENCY_SHIFT)    /* 001: One wait state */
+#    define FLASH_ACR_LATENCY_2     (2 << FLASH_ACR_LATENCY_SHIFT)    /* 010: Two wait states */
+#    define FLASH_ACR_LATENCY_3     (3 << FLASH_ACR_LATENCY_SHIFT)    /* 011: Three wait states */
+#    define FLASH_ACR_LATENCY_4     (4 << FLASH_ACR_LATENCY_SHIFT)    /* 100: Four wait states */
+#    define FLASH_ACR_LATENCY_5     (5 << FLASH_ACR_LATENCY_SHIFT)    /* 101: Five wait states */
+#    define FLASH_ACR_LATENCY_6     (6 << FLASH_ACR_LATENCY_SHIFT)    /* 110: Six wait states */
+#    define FLASH_ACR_LATENCY_7     (7 << FLASH_ACR_LATENCY_SHIFT)    /* 111: Seven wait states */
+
+#  if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#    define FLASH_ACR_HLFCYA        (1 << 3)  /* Bit 3: FLASH half cycle access */
+#    define FLASH_ACR_PRTFBE        (1 << 4)  /* Bit 4: FLASH prefetch enable */
+#    ifdef CONFIG_STM32_STM32F30XX
+#      define FLASH_ACR_PRFTBS      (1 << 5)  /* Bit 5: FLASH prefetch buffer status */
+#    endif
+#  elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#    define FLASH_ACR_PRFTEN        (1 << 8)  /* FLASH prefetch enable */
+#    define FLASH_ACR_ICEN          (1 << 9)  /* Bit 9: Instruction cache enable */
+#    define FLASH_ACR_DCEN          (1 << 10) /* Bit 10: Data cache enable */
+#    define FLASH_ACR_ICRST         (1 << 11) /* Bit 11: Instruction cache reset */
+#    define FLASH_ACR_DCRST         (1 << 12) /* Bit 12: Data cache reset */
 #  endif
-#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
-#  define FLASH_ACR_PRFTEN          (1 << 8)  /* FLASH prefetch enable */
-#  define FLASH_ACR_ICEN            (1 << 9)  /* Bit 9: Instruction cache enable */
-#  define FLASH_ACR_DCEN            (1 << 10) /* Bit 10: Data cache enable */
-#  define FLASH_ACR_ICRST           (1 << 11) /* Bit 11: Instruction cache reset */
-#  define FLASH_ACR_DCRST           (1 << 12) /* Bit 12: Data cache reset */
 #endif
 
 /* Flash Status Register (SR) */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
index 290ce867a..d30d9961c 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
@@ -94,7 +94,7 @@
 #define GPIO_ADC1_IN20      (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14)
 #define GPIO_ADC1_IN21      (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15)
 #define GPIO_ADC1_IN22      (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN7)
-#define GPIO_ADC1_IN24      (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN8)
+#define GPIO_ADC1_IN23      (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN8)
 #define GPIO_ADC1_IN24      (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN9)
 #define GPIO_ADC1_IN25      (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN10)
 
@@ -198,12 +198,6 @@
 /* Event outputs */
 
 #define GPIO_PA0_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN0)
-#define GPIO_PA10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN10)
-#define GPIO_PA10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN11)
-#define GPIO_PA11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN12)
-#define GPIO_PA13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN13)
-#define GPIO_PA14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN14)
-#define GPIO_PA15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN15)
 #define GPIO_PA1_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN1)
 #define GPIO_PA2_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN2)
 #define GPIO_PA3_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN3)
@@ -213,13 +207,13 @@
 #define GPIO_PA7_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN7)
 #define GPIO_PA8_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN8)
 #define GPIO_PA9_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_PA10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_PA11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_PA12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_PA13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN13)
+#define GPIO_PA14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_PA15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN15)
 #define GPIO_PB0_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN0)
-#define GPIO_PB10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN10)
-#define GPIO_PB11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN11)
-#define GPIO_PB12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN12)
-#define GPIO_PB13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN13)
-#define GPIO_PB14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN14)
-#define GPIO_PB15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN15)
 #define GPIO_PB1_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN1)
 #define GPIO_PB2_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN2)
 #define GPIO_PB3_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN3)
@@ -229,13 +223,13 @@
 #define GPIO_PB7_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN7)
 #define GPIO_PB8_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN8)
 #define GPIO_PB9_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_PB10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_PB11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN11)
+#define GPIO_PB12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_PB13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_PB14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_PB15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN15)
 #define GPIO_PC0_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN0)
-#define GPIO_PC10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN10)
-#define GPIO_PC11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN11)
-#define GPIO_PC12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN12)
-#define GPIO_PC13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN13)
-#define GPIO_PC14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN14)
-#define GPIO_PC15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN15)
 #define GPIO_PC1_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN1)
 #define GPIO_PC2_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN2)
 #define GPIO_PC3_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN3)
@@ -245,13 +239,13 @@
 #define GPIO_PC7_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN7)
 #define GPIO_PC8_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN8)
 #define GPIO_PC9_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN9)
+#define GPIO_PC10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN10)
+#define GPIO_PC11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN11)
+#define GPIO_PC12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN12)
+#define GPIO_PC13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN13)
+#define GPIO_PC14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN14)
+#define GPIO_PC15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN15)
 #define GPIO_PD0_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN0)
-#define GPIO_PD10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN10)
-#define GPIO_PD11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN11)
-#define GPIO_PD12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN12)
-#define GPIO_PD13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN13)
-#define GPIO_PD14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN14)
-#define GPIO_PD15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN15)
 #define GPIO_PD1_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN1)
 #define GPIO_PD2_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN2)
 #define GPIO_PD3_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN3)
@@ -261,13 +255,13 @@
 #define GPIO_PD7_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN7)
 #define GPIO_PD8_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN8)
 #define GPIO_PD9_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN9)
+#define GPIO_PD10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN10)
+#define GPIO_PD11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN11)
+#define GPIO_PD12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN12)
+#define GPIO_PD13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN13)
+#define GPIO_PD14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN14)
+#define GPIO_PD15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN15)
 #define GPIO_PE0_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN0)
-#define GPIO_PE10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN10)
-#define GPIO_PE11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN11)
-#define GPIO_PE12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN12)
-#define GPIO_PE13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN13)
-#define GPIO_PE14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN14)
-#define GPIO_PE15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN15)
 #define GPIO_PE1_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN1)
 #define GPIO_PE2_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN2)
 #define GPIO_PE3_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN3)
@@ -277,6 +271,12 @@
 #define GPIO_PE7_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN7)
 #define GPIO_PE8_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN8)
 #define GPIO_PE9_EVENT_OUT  (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN9)
+#define GPIO_PE10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN10)
+#define GPIO_PE11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN11)
+#define GPIO_PE12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN12)
+#define GPIO_PE13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN13)
+#define GPIO_PE14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN14)
+#define GPIO_PE15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN15)
 
 /* RTC */
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c
index bcae74306..562f326bb 100644
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c
@@ -528,7 +528,7 @@ int stm32_configgpio(uint32_t cfgset)
     {
       switch (cfgset & GPIO_SPEED_MASK)
         {
-#if define(CONFIG_STM32_STM32L15XX)
+#if defined(CONFIG_STM32_STM32L15XX)
           default:
           case GPIO_SPEED_400KHz:    /* 400 kHz Very low speed ouput */
             setting = GPIO_OSPEED_400KHz;
diff --git a/nuttx/arch/arm/src/stm32/stm32_lowputc.c b/nuttx/arch/arm/src/stm32/stm32_lowputc.c
index 968d9b5f6..49ac15e9a 100644
--- a/nuttx/arch/arm/src/stm32/stm32_lowputc.c
+++ b/nuttx/arch/arm/src/stm32/stm32_lowputc.c
@@ -546,7 +546,8 @@ void stm32_lowsetup(void)
 #endif /* HAVE_UART */
 }
 
-#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
+#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
+      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
 
 void stm32_lowsetup(void)
 {
diff --git a/nuttx/arch/arm/src/stm32/stm32_lse.c b/nuttx/arch/arm/src/stm32/stm32_lse.c
index 931199efd..8f2a52287 100644
--- a/nuttx/arch/arm/src/stm32/stm32_lse.c
+++ b/nuttx/arch/arm/src/stm32/stm32_lse.c
@@ -47,6 +47,18 @@
 /****************************************************************************
  * Definitions
  ****************************************************************************/
+/* The STM32L15XX family has no BDSR register.  The equivalent settings are
+ * in the CSR register for those chips.
+ */
+
+#ifdef CONFIG_STM32_STM32L15XX
+#  define STM32_RCC_BDCR       STM32_RCC_CSR
+#  define RCC_BDCR_LSEON       RCC_CSR_LSEON
+#  define RCC_BDCR_LSERDY      RCC_CSR_LSERDY
+#  define RCC_BDCR_RTCSEL_MASK RCC_CSR_RTCSEL_MASK
+#  define RCC_BDCR_RTCSEL_LSE  RCC_CSR_RTCSEL_LSE
+#  define RCC_BDCR_RTCEN       RCC_CSR_RTCEN
+#endif
 
 /****************************************************************************
  * Private Data
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c
index 6b98a5664..67dfea713 100644
--- a/nuttx/arch/arm/src/stm32/stm32_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c
@@ -76,14 +76,16 @@
 
 /* Include chip-specific clocking initialization logic */
 
-#if defined(CONFIG_STM32_STM32F10XX)
-#  include "chip/stm32f10xxx_rcc.c"
+#if defined(CONFIG_STM32_STM32L15XX)
+#  include "stm32l15xxx_rcc.c"
+#elif defined(CONFIG_STM32_STM32F10XX)
+#  include "stm32f10xxx_rcc.c"
 #elif defined(CONFIG_STM32_STM32F20XX)
-#  include "chip/stm32f20xxx_rcc.c"
+#  include "stm32f20xxx_rcc.c"
 #elif defined(CONFIG_STM32_STM32F30XX)
-#  include "chip/stm32f30xxx_rcc.c"
+#  include "stm32f30xxx_rcc.c"
 #elif defined(CONFIG_STM32_STM32F40XX)
-#  include "chip/stm32f40xxx_rcc.c"
+#  include "stm32f40xxx_rcc.c"
 #else
 #  error "Unsupported STM32 chip"
 #endif
diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c
index 4b5a9622a..4a06faee6 100644
--- a/nuttx/arch/arm/src/stm32/stm32_serial.c
+++ b/nuttx/arch/arm/src/stm32/stm32_serial.c
@@ -149,7 +149,8 @@
 #      error "UART8 DMA channel not defined (DMAMAP_UART8_RX)"
 #    endif
 
-#  elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#  elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
+        defined(CONFIG_STM32_STM32F30XX)
 
 #    if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
       defined(CONFIG_USART3_RXDMA)
@@ -184,7 +185,8 @@
 /* DMA priority */
 
 #  ifndef CONFIG_USART_DMAPRIO
-#    if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#    if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
+        defined(CONFIG_STM32_STM32F30XX)
 #      define CONFIG_USART_DMAPRIO  DMA_CCR_PRIMED
 #    elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #      define CONFIG_USART_DMAPRIO  DMA_SCR_PRIMED
@@ -192,7 +194,8 @@
 #      error "Unknown STM32 DMA"
 #    endif
 #  endif
-#    if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#    if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
+        defined(CONFIG_STM32_STM32F30XX)
 #    if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
 #      error "Illegal value for CONFIG_USART_DMAPRIO"
 #    endif
diff --git a/nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c
new file mode 100644
index 000000000..80b782758
--- /dev/null
+++ b/nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c
@@ -0,0 +1,557 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32l15xxx_rcc.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Allow up to 100 milliseconds for the high speed clock to become ready.
+ * that is a very long delay, but if the clock does not become ready we are
+ * hosed anyway.  Normally this is very fast, but I have seen at least one
+ * board that required this long, long timeout for the HSE to be ready.
+ */
+
+#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: rcc_reset
+ *
+ * Description:
+ *   Put all RCC registers in reset state
+ *
+ ****************************************************************************/
+
+static inline void rcc_reset(void)
+{
+  uint32_t regval;
+
+  putreg32(0, STM32_RCC_APB2RSTR);          /* Disable APB2 Peripheral Reset */
+  putreg32(0, STM32_RCC_APB1RSTR);          /* Disable APB1 Peripheral Reset */
+  putreg32(RCC_AHBENR_FLITFEN, STM32_RCC_AHBENR); /* FLITF Clock ON */
+  putreg32(0, STM32_RCC_APB2ENR);           /* Disable APB2 Peripheral Clock */
+  putreg32(0, STM32_RCC_APB1ENR);           /* Disable APB1 Peripheral Clock */
+
+  regval  = getreg32(STM32_RCC_CR);         /* Enable the HSI */
+  regval |= RCC_CR_HSION;
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CFGR);       /* Reset SW, HPRE, PPRE1, PPRE2, and MCO bits */
+  regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
+              RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCOSEL_MASK | RCC_CFGR_MCOPRE_MASK);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  regval  = getreg32(STM32_RCC_CR);         /* Disable the HSE and the PLL */
+  regval &= ~(RCC_CR_HSEON | RCC_CR_PLLON);
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CR);         /* Reset HSEBYP bit */
+  regval &= ~RCC_CR_HSEBYP;
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CFGR);       /* Reset PLLSRC, PLLXTPRE, PLLMUL, and PLLDIV bits */
+  regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK | RCC_CFGR_PLLDIV_MASK);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  putreg32(0, STM32_RCC_CIR);               /* Disable all interrupts */
+}
+
+/****************************************************************************
+ * Name: rcc_enableahb
+ *
+ * Description:
+ *   Enable selected AHB peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableahb(void)
+{
+  uint32_t regval;
+
+  /* Always enable FLITF clock clock */
+
+  regval  = RCC_AHBENR_FLITFEN;
+
+  /* Enable GPIOA-E, H, F-G (not all parts have all ports) */
+
+  regval |= (RCC_AHBENR_GPIOPAEN | RCC_AHBENR_GPIOPBEN | RCC_AHBENR_GPIOPCEN |
+             RCC_AHBENR_GPIOPDEN | RCC_AHBENR_GPIOPEEN | RCC_AHBENR_GPIOPHEN |
+             RCC_AHBENR_GPIOPFEN | RCC_AHBENR_GPIOPGEN);
+
+#ifdef CONFIG_STM32_CRC
+  /* CRC clock enable */
+
+  regval |= RCC_AHBENR_CRCEN;
+#endif
+
+#ifdef CONFIG_STM32_DMA1
+  /* DMA 1 clock enable */
+
+  regval |= RCC_AHBENR_DMA1EN;
+#endif
+
+#ifdef CONFIG_STM32_DMA2
+  /* DMA 2 clock enable */
+
+  regval |= RCC_AHBENR_DMA2EN;
+#endif
+
+#ifdef CONFIG_STM32_AES
+  /* AES clock enable */
+
+  regval |= RCC_AHBENR_AESEN;
+#endif
+
+#ifdef CONFIG_STM32_FSMC
+  /* FSMC clock enable */
+
+  regval |= RCC_AHBENR_FSMCEN;
+#endif
+
+  putreg32(regval, STM32_RCC_AHBENR);   /* Enable peripherals */
+}
+
+/****************************************************************************
+ * Name: rcc_enableapb1
+ *
+ * Description:
+ *   Enable selected APB1 peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableapb1(void)
+{
+  uint32_t regval;
+
+  /* Set the appropriate bits in the APB1ENR register to enabled the
+   * selected APB1 peripherals.
+   */
+
+  regval  = getreg32(STM32_RCC_APB1ENR);
+
+#ifdef CONFIG_STM32_TIM2
+  /* Timer 2 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM2EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM3
+  /* Timer 3 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM3EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM4
+  /* Timer 4 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM4EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM5
+  /* Timer 5 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM5EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM6
+  /* Timer 6 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM6EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM7
+  /* Timer 7 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM7EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_LCD
+  /* LCD clock enable */
+
+  regval |= RCC_APB1ENR_LCDEN;
+#endif
+
+#ifdef CONFIG_STM32_WWDG
+  /* Window Watchdog clock enable */
+
+  regval |= RCC_APB1ENR_WWDGEN;
+#endif
+
+#ifdef CONFIG_STM32_SPI2
+  /* SPI 2 clock enable */
+
+  regval |= RCC_APB1ENR_SPI2EN;
+#endif
+
+#ifdef CONFIG_STM32_SPI3
+  /* SPI 3 clock enable */
+
+  regval |= RCC_APB1ENR_SPI3EN;
+#endif
+
+#ifdef CONFIG_STM32_USART2
+  /* USART 2 clock enable */
+
+  regval |= RCC_APB1ENR_USART2EN;
+#endif
+
+#ifdef CONFIG_STM32_USART3
+  /* USART 3 clock enable */
+
+  regval |= RCC_APB1ENR_USART3EN;
+#endif
+
+#ifdef CONFIG_STM32_USART4
+  /* USART 4 clock enable */
+
+  regval |= RCC_APB1ENR_USART4EN;
+#endif
+
+#ifdef CONFIG_STM32_USART5
+  /* USART 5 clock enable */
+
+  regval |= RCC_APB1ENR_USART5EN;
+#endif
+
+#ifdef CONFIG_STM32_I2C1
+  /* I2C 1 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_I2C1EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_I2C2
+  /* I2C 2 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_I2C2EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_USB
+  /* USB clock enable */
+
+  regval |= RCC_APB1ENR_USBEN;
+#endif
+
+#ifdef CONFIG_STM32_PWR
+  /*  Power interface clock enable */
+
+  regval |= RCC_APB1ENR_PWREN;
+#endif
+
+#ifdef CONFIG_STM32_DAC
+  /* DAC interface clock enable */
+
+  regval |= RCC_APB1ENR_DACEN;
+#endif
+
+#ifdef CONFIG_STM32_COMP
+  /* COMP interface clock enable */
+
+  regval |= RCC_APB1ENR_COMPEN;
+#endif
+
+  putreg32(regval, STM32_RCC_APB1ENR);
+}
+
+/****************************************************************************
+ * Name: rcc_enableapb2
+ *
+ * Description:
+ *   Enable selected APB2 peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableapb2(void)
+{
+  uint32_t regval;
+
+  /* Set the appropriate bits in the APB2ENR register to enabled the
+   * selected APB2 peripherals.
+   */
+
+  regval = getreg32(STM32_RCC_APB2ENR);
+
+#ifdef CONFIG_STM32_SYSCFG
+  /* SYSCFG clock */
+
+  regval |= RCC_APB2ENR_SYSCFGEN;
+#endif
+
+#ifdef CONFIG_STM32_TIM9
+  /* TIM9 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM9EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM10
+  /* TIM10 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM10EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM11
+  /* TIM11 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM11EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_ADC1
+  /* ADC 1 clock enable */
+
+  regval |= RCC_APB2ENR_ADC1EN;
+#endif
+
+#ifdef CONFIG_STM32_SDIO
+  /* SDIO clock enable */
+
+  regval |= RCC_APB2ENR_SDIOEN;
+#endif
+
+#ifdef CONFIG_STM32_SPI1
+  /* SPI 1 clock enable */
+
+  regval |= RCC_APB2ENR_SPI1EN;
+#endif
+
+#ifdef CONFIG_STM32_USART1
+  /* USART1 clock enable */
+
+  regval |= RCC_APB2ENR_USART1EN;
+#endif
+
+  putreg32(regval, STM32_RCC_APB2ENR);
+}
+
+/****************************************************************************
+ * Name: stm32_rcc_enablehse
+ *
+ * Description:
+ *   Enable the External High-Speed (HSE) Oscillator.
+ *
+ ****************************************************************************/
+
+#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
+static inline bool stm32_rcc_enablehse(void)
+{
+  uint32_t regval;
+  volatile int32_t timeout;
+
+  /* Enable External High-Speed Clock (HSE) */
+
+  regval  = getreg32(STM32_RCC_CR);
+  regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
+  regval |= RCC_CR_HSEON;           /* Enable HSE */
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the HSE is ready (or until a timeout elapsed) */
+
+  for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      /* Check if the HSERDY flag is the set in the CR */
+
+      if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
+        {
+          /* If so, then break-out with timeout > 0 */
+
+          break;
+        }
+    }
+
+  /* In the case of a timeout starting the HSE, we really don't have a
+   * strategy.  This is almost always a hardware failure or misconfiguration.
+   */
+
+  return timeout > 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_stdclockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on settings in board.h.
+ *
+ *   NOTE:  This logic would need to be extended if you need to select low-
+ *   power clocking modes or any clocking other than PLL driven by the HSE.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
+static void stm32_stdclockconfig(void)
+{
+  uint32_t regval;
+
+  /* If the PLL is using the HSE, or the HSE is the system clock */
+
+#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
+  /* Enable HSE clocking */
+
+  if (!stm32_rcc_enablehse())
+    {
+      /* In the case of a timeout starting the HSE, we really don't have a
+       * strategy.  This is almost always a hardware failure or misconfiguration.
+       */
+
+      return;
+    }
+#endif
+
+  /* Increasing the CPU frequency (in the same voltage range):
+   *
+   * After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the
+   * FLASH_ACR register. 32-bit access is enabled and prefetch is disabled.
+   * ST strongly recommends to use the following software sequences to tune the
+   * number of wait states needed to access the Flash memory with the CPU
+   * frequency.
+   *
+   *   - Program the 64-bit access by setting the ACC64 bit in Flash access
+   *     control register (FLASH_ACR)
+   *   - Check that 64-bit access is taken into account by reading FLASH_ACR
+   *   - Program 1 WS to the LATENCY bit in FLASH_ACR
+   *   - Check that the new number of WS is taken into account by reading FLASH_ACR
+   *   - Modify the CPU clock source by writing to the SW bits in the Clock
+   *     configuration register (RCC_CFGR)
+   *   - If needed, modify the CPU clock prescaler by writing to the HPRE bits in
+   *     RCC_CFGR
+   *   - Check that the new CPU clock source or/and the new CPU clock prescaler
+   *     value is/are taken into account by reading the clock source status (SWS
+   *     bits) or/and the AHB prescaler value (HPRE bits), respectively, in the
+   *     RCC_CFGR register
+   */
+ 
+  regval = getreg32(STM32_FLASH_ACR);
+  regval |= FLASH_ACR_ACC64;          /* 64-bit access mode */
+  putreg32(regval, STM32_FLASH_ACR);
+
+  regval |= FLASH_ACR_LATENCY;        /* One wait state */
+  putreg32(regval, STM32_FLASH_ACR);
+
+  /* Enable FLASH prefetch */
+
+  regval |= FLASH_ACR_PRFTEN;
+  putreg32(regval, STM32_FLASH_ACR);
+
+  /* Set the HCLK source/divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_HPRE_MASK;
+  regval |= STM32_RCC_CFGR_HPRE;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK2 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE2_MASK;
+  regval |= STM32_RCC_CFGR_PPRE2;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK1 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE1_MASK;
+  regval |= STM32_RCC_CFGR_PPRE1;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* If we are using the PLL, configure and start it */
+
+#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
+
+  /* Set the PLL divider and multipler */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
+  regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLMUL | STM32_CFGR_PLLDIV);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Enable the PLL */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLLON;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the PLL is ready */
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
+
+#endif
+
+  /* Select the system clock source (probably the PLL) */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_SW_MASK;
+  regval |= STM32_SYSCLK_SW;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Wait until the selected source is used as the system clock source */
+
+  while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
+}
+#endif
+
+/****************************************************************************
+ * Name: rcc_enableperiphals
+ ****************************************************************************/
+
+static inline void rcc_enableperipherals(void)
+{
+  rcc_enableahb();
+  rcc_enableapb2();
+  rcc_enableapb1();
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/