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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2008-11-02 19:37:20 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2008-11-02 19:37:20 +0000 |
| commit | 1b4bb7ad9182132f8dc3e6ba0be86d1ae401f8e8 (patch) | |
| tree | cbe9e9f8301b8a306175eafeb7a50adc44ca4e29 /nuttx/arch/arm/src/str71x/str71x_serial.c | |
| parent | 11a33e587907ffd9a3a485111b76437df692fd99 (diff) | |
| download | px4-nuttx-1b4bb7ad9182132f8dc3e6ba0be86d1ae401f8e8.tar.gz px4-nuttx-1b4bb7ad9182132f8dc3e6ba0be86d1ae401f8e8.tar.bz2 px4-nuttx-1b4bb7ad9182132f8dc3e6ba0be86d1ae401f8e8.zip | |
Move handle clock macros into a header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1120 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/str71x/str71x_serial.c')
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_serial.c | 25 |
1 files changed, 2 insertions, 23 deletions
diff --git a/nuttx/arch/arm/src/str71x/str71x_serial.c b/nuttx/arch/arm/src/str71x/str71x_serial.c index 72514324c..e9739ec62 100644 --- a/nuttx/arch/arm/src/str71x/str71x_serial.c +++ b/nuttx/arch/arm/src/str71x/str71x_serial.c @@ -52,6 +52,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" +#include "str71x_internal.h" #ifdef CONFIG_USE_SERIALDRIVER @@ -181,28 +182,6 @@ # warning "No CONFIG_UARTn_SERIAL_CONSOLE Setting" #endif -/* Calculate the value of PCLK1 from settings in board.h. - * - * Example: - * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2) - * CLK2 = 4MHz - * PLL1OUT = 16 * CLK2 / 2 = 32MHz - * CLK3 = 32MHz - * RCLK = 32MHz - * PCLK1 = 32MHz / 1 = 32MHz - */ - -#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */ -# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */ -#else -# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */ -#endif - /* PLL1OUT derives from CLK2 */ -#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV) -#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */ -#define RCLK CLK3 /* RCLK hard coded to be CLK3 */ -#define PCLK1 (RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */ - /**************************************************************************** * Private Types ****************************************************************************/ @@ -486,7 +465,7 @@ static int up_setup(struct uart_dev_s *dev) /* Set the BAUD rate */ divisor = 16 * priv->baud; - baud = (PCLK1 + divisor/2) / divisor; + baud = (STR71X_PCLK1 + divisor/2) / divisor; up_serialout(priv, STR71X_UART_BR_OFFSET, baud); /* Get mode setting */ |