diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-05-30 18:39:50 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-05-30 18:39:50 +0000 |
| commit | 1055f3808a1e79fb8f49517e1d071dbee5003433 (patch) | |
| tree | 30950b3d24c3a5c894f23a7bc8e542a33f1aa243 /nuttx/arch/arm/src | |
| parent | 9d7572eb7ab663d4ca4b0ce7d29fc2ecc03230d3 (diff) | |
| download | px4-nuttx-1055f3808a1e79fb8f49517e1d071dbee5003433.tar.gz px4-nuttx-1055f3808a1e79fb8f49517e1d071dbee5003433.tar.bz2 px4-nuttx-1055f3808a1e79fb8f49517e1d071dbee5003433.zip | |
Add QEI and MC PWM header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2718 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src')
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h | 251 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_qei.h | 221 |
2 files changed, 472 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h b/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h new file mode 100755 index 000000000..7c109dd4e --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h @@ -0,0 +1,251 @@ +/************************************************************************************
+ * arch/arm/src/lpc17xx/lpc17_mcpwm.h
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H
+#define __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "lp17_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */
+#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */
+#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */
+#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */
+#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */
+#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */
+#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */
+#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */
+#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */
+#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */
+#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */
+#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */
+#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */
+#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */
+#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */
+#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */
+#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */
+#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */
+#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */
+#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */
+#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */
+#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */
+#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */
+#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */
+#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */
+#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */
+#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */
+#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */
+#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */
+#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */
+
+/* Register addresses ***************************************************************/
+
+#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET)
+#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET)
+#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET)
+#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET)
+#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET)
+#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET)
+#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET)
+#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET)
+#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET)
+#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET)
+#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET)
+#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET)
+#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET)
+#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET)
+#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET)
+#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET)
+#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET)
+#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET)
+#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET)
+#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET)
+#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET)
+#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET)
+#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET)
+#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET)
+#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET)
+#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET)
+#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET)
+#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET)
+#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET)
+#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* PWM Control read address */
+
+#define MCPWM_CON_
+
+/* PWM Control set address */
+
+#define MCPWM_CONSET_
+
+/* PWM Control clear address */
+
+#define MCPWM_CONCLR_
+
+/* Capture Control read address */
+
+#define MCPWM_CAPCON_
+
+/* Capture Control set address */
+
+#define MCPWM_CAPCONSET_
+
+/* Event Control clear address */
+
+#define MCPWM_CAPCONCLR_
+
+/* Timer Counter register, channel 0 */
+
+#define MCPWM_TC0_
+
+/* Timer Counter register, channel 1 */
+
+#define MCPWM_TC1_
+
+/* Timer Counter register, channel 2 */
+
+#define MCPWM_TC2_
+
+/* Limit register, channel 0 */
+
+#define MCPWM_LIM0_
+
+/* Limit register, channel 1 */
+
+#define MCPWM_LIM1_
+
+/* Limit register, channel 2 */
+
+#define MCPWM_LIM2_
+
+/* Match register, channel 0 */
+
+#define MCPWM_MAT0_
+
+/* Match register, channel 1 */
+
+#define MCPWM_MAT1_
+
+/* Match register, channel 2 */
+
+#define MCPWM_MAT2_
+
+/* Dead time register */
+
+#define MCPWM_DT_
+
+/* Commutation Pattern register */
+
+#define MCPWM_CP_
+
+/* Capture register, channel 0 */
+
+#define MCPWM_CAP0_
+
+/* Capture register, channel 1 */
+
+#define MCPWM_CAP1_
+
+/* Capture register, channel 2 */
+
+#define MCPWM_CAP2_
+
+/* Interrupt Enable read address */
+
+#define MCPWM_INTEN_
+
+/* Interrupt Enable set address */
+
+#define MCPWM_INTENSET_
+
+/* Interrupt Enable clear address */
+
+#define MCPWM_INTENCLR_
+
+/* Count Control read address */
+
+#define MCPWM_CNTCON_
+
+/* Count Control set address */
+
+#define MCPWM_CNTCONSET_
+
+/* Count Control clear address */
+
+#define MCPWM_CNTCONCLR_
+
+/* Interrupt flags read address */
+
+#define MCPWM_INTF_
+
+/* Interrupt flags set address */
+
+#define MCPWM_INTFSET_
+
+/* Interrupt flags clear address */
+
+#define MCPWM_INTFCLR_
+
+/* Capture clear address */
+
+#define MCPWM_CAPCLR_
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H */
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h new file mode 100755 index 000000000..470cd03cc --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h @@ -0,0 +1,221 @@ +/************************************************************************************
+ * arch/arm/src/lpc17xx/lpc17_qei.h
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H
+#define __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "lp17_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+/* Control registers */
+
+#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */
+#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */
+#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */
+
+/* Position, index, and timer registers */
+
+#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */
+#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */
+#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */
+#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */
+#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */
+#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */
+#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */
+#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */
+#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */
+#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */
+#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */
+#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
+#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */
+
+/* Interrupt registers */
+
+#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */
+#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */
+#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
+#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */
+#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */
+#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */
+
+/* Register addresses ***************************************************************/
+/* Control registers */
+
+#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET)
+#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET)
+#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET)
+
+/* Position, index, and timer registers */
+
+#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET)
+#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET)
+#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET)
+#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET)
+#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET)
+#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET)
+#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET)
+#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET)
+#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET)
+#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET)
+#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET)
+#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET)
+#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET)
+
+/* Interrupt registers */
+
+#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET)
+#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET)
+#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET)
+#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET)
+#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET)
+#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* Control registers */
+
+/* Control register */
+
+#define QEI_CON_
+
+/* Encoder status register */
+
+#define QEI_STAT_
+
+/* Configuration register */
+
+#define QEI_CONF_
+
+/* Position, index, and timer registers */
+/* Position register */
+
+#define QEI_POS_
+
+/* Maximum position register */
+
+#define QEI_MAXPOS_
+
+/* Position compare register */
+
+#define QEI_CMPOS0_
+
+/* Position compare register */
+
+#define QEI_CMPOS1_
+
+/* Position compare register */
+
+#define QEI_CMPOS2_
+
+/* Index count register */
+
+#define QEI_INXCNT_
+
+/* Index compare register */
+
+#define QEI_INXCMP_
+
+/* Velocity timer reload register */
+
+#define QEI_LOAD_
+
+/* Velocity timer register */
+
+#define QEI_TIME_
+
+/* Velocity counter register */
+
+#define QEI_VEL_
+
+/* Velocity capture register */
+
+#define QEI_CAP_
+
+/* Velocity compare register */
+
+#define QEI_VELCOMP_
+
+/* Digital filter register */
+
+#define QEI_FILTER_
+
+/* Interrupt registers */
+/* Interrupt enable clear register */
+
+#define QEI_IEC_
+
+/* Interrupt enable set register */
+
+#define QEI_IES_
+
+/* Interrupt status register */
+
+#define QEI_INTSTAT_
+
+/* Interrupt enable register */
+
+#define QEI_IE_
+
+/* Interrupt status clear register */
+
+#define QEI_CLR_
+
+/* Interrupt status set register */
+
+#define QEI_SET_
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H */
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