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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-08 14:42:18 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-08 14:42:18 +0000 |
| commit | 1442e62637fa138626671be49b51d5329c6536c3 (patch) | |
| tree | 37cca4e1b7020da95999bce0c162a6ba2069305c /nuttx/arch/arm/src | |
| parent | 0017d65ee25f15e67e5376ac59340e5835032867 (diff) | |
| download | px4-nuttx-1442e62637fa138626671be49b51d5329c6536c3.tar.gz px4-nuttx-1442e62637fa138626671be49b51d5329c6536c3.tar.bz2 px4-nuttx-1442e62637fa138626671be49b51d5329c6536c3.zip | |
More stm32f3discovery updates
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5624 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_dumpgpio.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c index cd1933831..393467b19 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c @@ -120,9 +120,12 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ flags = irqsave(); + #if defined(CONFIG_STM32_STM32F10XX) + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); + if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) { lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n", @@ -143,11 +146,38 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) lldbg(" GPIO%c not enabled: APB2ENR: %08x\n", g_portchar[port], getreg32(STM32_RCC_APB2ENR)); } + +#elif defined(CONFIG_STM32_STM32F30XX) + + DEBUGASSERT(port < STM32_NGPIO_PORTS); + + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + + /* GPIOs are always enabled */ + + lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + lldbg(" AFRH: %08x AFRL: %08x BRR: %04x\n", + getreg32(base + STM32_GPIO_ARFH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET), + getreg32(base + STM32_GPIO_BRR_OFFSET)); + #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) + DEBUGASSERT(port < STM32_NGPIO_PORTS); lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); + if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) { lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", |