Add initial CC1101 wireless logic from Uros

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3617 42af7a65-404d-4744-a932-0658087f49c3

8 files changed, 332 insertions, 109 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_exti.h b/nuttx/arch/arm/src/stm32/chip/stm32_exti.h
new file mode 100644
index 000000000..b16a334c9
--- /dev/null
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_exti.h
@@ -0,0 +1,109 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32_exti.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define STM32_NEXTI            20
+#  define STM32_EXTI_MASK        0x000fffff
+#else
+#  define STM32_NEXTI            19
+#  define STM32_EXTI_MASK        0x0007ffff
+#endif
+
+#define STM32_EXTI_BIT(n)        (1 << (n))
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_EXTI_IMR_OFFSET    0x0000  /* Interrupt mask register */
+#define STM32_EXTI_EMR_OFFSET    0x0004  /* Event mask register */
+#define STM32_EXTI_RTSR_OFFSET   0x0008  /* Rising Trigger selection register */
+#define STM32_EXTI_FTSR_OFFSET   0x000c  /* Falling Trigger selection register */
+#define STM32_EXTI_SWIER_OFFSET  0x0010  /* Software interrupt event register */
+#define STM32_EXTI_PR_OFFSET     0x0014  /* Pending register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_EXTI_IMR          (STM32_EXTI_BASE+STM32_EXTI_IMR_OFFSET)
+#define STM32_EXTI_EMR          (STM32_EXTI_BASE+STM32_EXTI_EMR_OFFSET)
+#define STM32_EXTI_RTSR         (STM32_EXTI_BASE+STM32_EXTI_RTSR_OFFSET)
+#define STM32_EXTI_FTSR         (STM32_EXTI_BASE+STM32_EXTI_FTSR_OFFSET)
+#define STM32_EXTI_SWIER        (STM32_EXTI_BASE+STM32_EXTI_SWIER_OFFSET)
+#define STM32_EXTI_PR           (STM32_EXTI_BASE+STM32_EXTI_PR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Interrupt mask register */
+
+#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Interrupt Mask on line n */
+#define EXTI_IMR_MASK            STM32_EXTI_MASK
+
+/* Event mask register */
+
+#define EXTI_EMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_EMR_SHIFT           (0)     /* Bits 18/19-0:  Event Mask on line n */
+#define EXTI_EMR_MASK            STM32_EXTI_MASK
+
+/* Rising Trigger selection register */
+
+#define EXTI_RTSR_BIT(n)         STM32_EXTI_BIT(n)
+#define EXTI_RTSR_SHIFT          (0)     /* Bits 18/19-0: Rising trigger event configuration bit of line n */
+#define EXTI_RTSR_MASK           STM32_EXTI_MASK
+
+/* Falling Trigger selection register */
+
+#define EXTI_FTSR_BIT(n)         STM32_EXTI_BIT(n)
+#define EXTI_FTSR_SHIFT          (0)     /* Bits 18/19-0: Falling trigger event configuration bit of line n */
+#define EXTI_FTSR_MASK           STM32_EXTI_MASK
+
+/* Software interrupt event register  */
+
+#define EXTI_SWIER_BIT(n)        STM32_EXTI_BIT(n)
+#define EXTI_SWIER_SHIFT         (0)     /*  Bits 18/19-0: Software Interrupt on line n */
+#define EXTI_SWIER_MASK          STM32_EXTI_MASK
+
+/* Pending register */
+
+#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Pending bit on line x */
+#define EXTI_IMR_MASK            STM32_EXTI_MASK
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32_gpio.h
index 3de353efc..59d0ddf94 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_gpio.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_gpio.h
@@ -54,7 +54,7 @@
 
 #define STM32_AFIO_EVCR_OFFSET       0x0000  /* Event control register */
 #define STM32_AFIO_MAPR_OFFSET       0x0004  /* AF remap and debug I/O configuration register */
-#define STM32_AFIO_EXTICR_OFFSET(p)  (0x0008 + ((p) >> 2))
+#define STM32_AFIO_EXTICR_OFFSET(p)  (0x0008 + ((p) & 0xC)) /* Registers are displaced by 4! */
 #define STM32_AFIO_EXTICR1_OFFSET    0x0008  /* External interrupt configuration register 1 */
 #define STM32_AFIO_EXTICR2_OFFSET    0x000c  /* External interrupt configuration register 2 */
 #define STM32_AFIO_EXTICR3_OFFSET    0x0010  /* External interrupt configuration register 3 */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h
index a41001525..7c33da449 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h
@@ -266,6 +266,11 @@
 #  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
 #endif
 
+#define GPIO_SPI2_NSS       (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SPI2_SCK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_SPI2_MISO      (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_SPI2_MOSI      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+
 #if defined(CONFIG_STM32_SPI3_REMAP)
 #  define GPIO_SPI3_NSS     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
 #  define GPIO_SPI3_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
diff --git a/nuttx/arch/arm/src/stm32/stm32_exti.h b/nuttx/arch/arm/src/stm32/stm32_exti.h
index b0e0329c2..8221ccb2d 100644
--- a/nuttx/arch/arm/src/stm32/stm32_exti.h
+++ b/nuttx/arch/arm/src/stm32/stm32_exti.h
@@ -36,88 +36,9 @@
 #ifndef __ARCH_ARM_SRC_STM32_STM32_EXTI_H
 #define __ARCH_ARM_SRC_STM32_STM32_EXTI_H
 
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
 #include <nuttx/config.h>
 
 #include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_CONNECTIVITYLINE
-#  define STM32_NEXTI            20
-#  define STM32_EXTI_MASK        0x000fffff
-#else
-#  define STM32_NEXTI            19
-#  define STM32_EXTI_MASK        0x0007ffff
-#endif
-
-#define STM32_EXTI_BIT(n)        (1 << (n))
-
-/* Register Offsets *****************************************************************/
-
-#define STM32_EXTI_IMR_OFFSET    0x0000  /* Interrupt mask register */
-#define STM32_EXTI_EMR_OFFSET    0x0004  /* Event mask register */
-#define STM32_EXTI_RTSR_OFFSET   0x0008  /* Rising Trigger selection register */
-#define STM32_EXTI_FTSR_OFFSET   0x000c  /* Falling Trigger selection register */
-#define STM32_EXTI_SWIER_OFFSET  0x0010  /* Software interrupt event register */
-#define STM32_EXTI_PR_OFFSET     0x0014  /* Pending register */
-
-/* Register Addresses ***************************************************************/
-
-
-/* Register Bitfield Definitions ****************************************************/
-
-/* Interrupt mask register */
-
-#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
-#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Interrupt Mask on line n */
-#define EXTI_IMR_MASK            STM32_EXTI_MASK
-
-/* Event mask register */
-
-#define EXTI_EMR_BIT(n)          STM32_EXTI_BIT(n)
-#define EXTI_EMR_SHIFT           (0)     /* Bits 18/19-0:  Event Mask on line n */
-#define EXTI_EMR_MASK            STM32_EXTI_MASK
-
-/* Rising Trigger selection register */
-
-#define EXTI_RTSR_BIT(n)         STM32_EXTI_BIT(n)
-#define EXTI_RTSR_SHIFT          (0)     /* Bits 18/19-0: Rising trigger event configuration bit of line n */
-#define EXTI_RTSR_MASK           STM32_EXTI_MASK
-
-/* Falling Trigger selection register */
-
-#define EXTI_FTSR_BIT(n)         STM32_EXTI_BIT(n)
-#define EXTI_FTSR_SHIFT          (0)     /* Bits 18/19-0: Falling trigger event configuration bit of line n */
-#define EXTI_FTSR_MASK           STM32_EXTI_MASK
-
-/* Software interrupt event register  */
-
-#define EXTI_SWIER_BIT(n)        STM32_EXTI_BIT(n)
-#define EXTI_SWIER_SHIFT         (0)     /*  Bits 18/19-0: Software Interrupt on line n */
-#define EXTI_SWIER_MASK          STM32_EXTI_MASK
-
-/* Pending register */
-
-#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
-#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Pending bit on line x */
-#define EXTI_IMR_MASK            STM32_EXTI_MASK
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+#include "chip/stm32_exti.h"
 
 #endif /* __ARCH_ARM_SRC_STM32_STM32_EXTI_H */
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c
index 963e6286e..85a8d558f 100755
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c
@@ -1,8 +1,10 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32_gpio.c
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *           Uros Platise <uros.platise@isotel.eu>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -39,6 +41,8 @@
  **/
 
 #include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -48,6 +52,7 @@
 #include "up_arch.h"
 #include "chip.h"
 #include "stm32_gpio.h"
+#include "stm32_exti.h"
 #include "stm32_rcc.h"
 #include "stm32_internal.h"
 
@@ -82,9 +87,15 @@ static const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
 };
 
 #ifdef CONFIG_DEBUG
-static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+static const char g_portchar[8] = { 
+    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' 
+};
 #endif
 
+static void (*stm32_exti_callbacks[7])(void) = {
+    NULL, NULL, NULL, NULL, NULL, NULL, NULL
+};
+
 
 /****************************************************************************
  * Private Functions
@@ -209,6 +220,7 @@ int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
           shift   = AFIO_EXTICR_EXTI_SHIFT(pin);
           regval &= ~(AFIO_EXTICR_PORT_MASK << shift);
           regval |= (((uint32_t)port) << shift);
+          
           putreg32(regval, regaddr);
         }
 
@@ -246,12 +258,84 @@ int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
 
 
 /****************************************************************************
+ * Interrupt Service Routines - Dispatchers
+ ****************************************************************************/
+
+int stm32_exti0_isr(int irq, void *context)
+{
+    putreg32(0x0001, STM32_EXTI_PR);
+    if (stm32_exti_callbacks[0]) stm32_exti_callbacks[0]();
+    return 0;
+}
+
+
+int stm32_exti1_isr(int irq, void *context)
+{
+    putreg32(0x0002, STM32_EXTI_PR);
+    if (stm32_exti_callbacks[1]) stm32_exti_callbacks[1]();
+    return 0;
+}
+
+
+int stm32_exti2_isr(int irq, void *context)
+{
+    putreg32(0x0004, STM32_EXTI_PR);
+    if (stm32_exti_callbacks[2]) stm32_exti_callbacks[2]();
+    return 0;
+}
+
+
+int stm32_exti3_isr(int irq, void *context)
+{
+    putreg32(0x0008, STM32_EXTI_PR);
+    if (stm32_exti_callbacks[3]) stm32_exti_callbacks[3]();
+    return 0;
+}
+
+
+int stm32_exti4_isr(int irq, void *context)
+{
+    putreg32(0x0010, STM32_EXTI_PR);
+    if (stm32_exti_callbacks[4]) stm32_exti_callbacks[4]();
+    return 0;
+}
+
+
+int stm32_exti95_isr(int irq, void *context)
+{
+    putreg32(0x03E0, STM32_EXTI_PR);    /* ACK all pins, since we support just one */
+    if (stm32_exti_callbacks[5]) stm32_exti_callbacks[5]();
+    return 0;
+}
+
+
+int stm32_exti1510_isr(int irq, void *context)
+{
+    putreg32(0xFC00, STM32_EXTI_PR);    /* ACK all pins, since we support just one */
+    if (stm32_exti_callbacks[6]) stm32_exti_callbacks[6]();
+    return 0;
+}
+
+
+/****************************************************************************
  * Public Functions
  ****************************************************************************/
 
-void stm32_gpio_remap(void)
+/************************************************************************************
+ * Function:  stm32_gpioinit
+ *
+ * Description:
+ *   Based on configuration within the .config file, it does:
+ *    - Remaps positions of alternative functions. 
+ * 
+ * Typically called from stm32_start().
+ ************************************************************************************/
+
+void stm32_gpioinit(void)
 {
-  uint32_t val = 0;
+    /* Remap according to the configuration within .config file */
+
+    uint32_t val = 0;
 
 #ifdef CONFIG_STM32_JTAG_FULL_ENABLE
     // the reset default
@@ -318,7 +402,7 @@ void stm32_gpio_remap(void)
     val |= AFIO_MAPR_PD01;
 #endif
 
-  putreg32(val, STM32_AFIO_MAPR);
+    putreg32(val, STM32_AFIO_MAPR);  
 }
 
 
@@ -446,6 +530,94 @@ bool stm32_gpioread(uint32_t pinset)
   return 0;
 }
 
+/************************************************************************************
+ * Name: stm32_gpiosetevent
+ *
+ * Description:
+ *   Sets/clears GPIO based event and interrupt triggers.
+ * 
+ * Limitations:
+ *   Presently single gpio can configured on the same EXTI line.
+ * 
+ * Parameters:
+ *  - pinset: gpio pin configuration
+ *  - rising/falling edge: enables
+ *  - event:  generate event when set
+ *  - func:   when non-NULL, generate interrupt
+ * 
+ * Returns: 
+ *  True when GPIO Event/Interrupt generation is successfully configured.
+ ************************************************************************************/
+
+bool stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, 
+                       bool event, void (*func)(void))
+{
+    uint32_t exti_isr = pinset & GPIO_PIN_MASK;
+    uint32_t exti_bit = STM32_EXTI_BIT( exti_isr );
+    int      intno;
+    int      (*exti_hnd)(int irq, void *context);
+    
+    /* Set callback, single callback at the moment, but we could extend
+     * that easily 
+     */
+    
+    if (exti_isr < 5) {
+        intno    = exti_isr + STM32_IRQ_EXTI0;
+        switch(exti_isr) {
+            case 0: exti_hnd = stm32_exti0_isr; break;
+            case 1: exti_hnd = stm32_exti1_isr; break;
+            case 2: exti_hnd = stm32_exti2_isr; break;
+            case 3: exti_hnd = stm32_exti3_isr; break;
+            default:exti_hnd = stm32_exti4_isr; break;
+        }
+    }
+    else if (exti_isr < 10) {
+        exti_isr = 5;
+        exti_hnd = stm32_exti95_isr;
+        intno    = STM32_IRQ_EXTI95;
+    }
+    else {
+        exti_isr = 6;
+        exti_hnd = stm32_exti1510_isr;
+        intno    = STM32_IRQ_EXTI1510;
+    }
+    
+    /* Check if previous and different instance exists? */
+    
+    if (func && stm32_exti_callbacks[exti_isr] &&
+        func != stm32_exti_callbacks[exti_isr]) 
+        return false;
+
+    stm32_exti_callbacks[exti_isr] = func;
+
+    /* Install external interrupt handlers */
+    
+    if (func) {
+        irq_attach(intno, exti_hnd);
+        up_enable_irq(intno);
+    }
+    else up_disable_irq(intno);
+    
+    /* Configure GPIO, enable EXTI line enabled if event or interrupt is enabled */
+    
+    if (event || func) 
+        pinset |= GPIO_EXTI;
+        
+    stm32_configgpio( pinset );
+    
+    /* Configure rising/falling edges */
+    
+    modifyreg32(STM32_EXTI_RTSR, risingedge ? 0 : exti_bit, risingedge ? exti_bit : 0);
+    modifyreg32(STM32_EXTI_FTSR, fallingedge ? 0 : exti_bit, fallingedge ? exti_bit : 0);
+    
+    /* Enable Events and Interrupts */
+    
+    modifyreg32(STM32_EXTI_EMR, event ? 0 : exti_bit, event ? exti_bit : 0);
+    modifyreg32(STM32_EXTI_IMR, func ? 0 : exti_bit, func ? exti_bit : 0);
+        
+    return true;
+}
+
 /****************************************************************************
  * Function:  stm32_dumpgpio
  *
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h
index abced5304..cc2745866 100644
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.h
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h
@@ -2,7 +2,9 @@
  * arch/arm/src/stm32/stm32_gpio.h
  *
  *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *           Uros Platise <uros.platise@isotel.eu>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -221,6 +223,28 @@ EXTERN void stm32_gpiowrite(uint32_t pinset, bool value);
 EXTERN bool stm32_gpioread(uint32_t pinset);
 
 /************************************************************************************
+ * Name: stm32_gpiosetevent
+ *
+ * Description:
+ *   Sets/clears GPIO based event and interrupt triggers.
+ * 
+ * Limitations:
+ *   Presently single gpio can configured on the same EXTI line.
+ * 
+ * Parameters:
+ *  - pinset: gpio pin configuration
+ *  - rising/falling edge: enables
+ *  - event:  generate event when set
+ *  - func:   when non-NULL, generate interrupt
+ * 
+ * Returns: 
+ *  True when GPIO Event/Interrupt generation is successfully configured.
+ ************************************************************************************/
+
+EXTERN bool stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, 
+                       bool event, void (*func)(void));
+
+/************************************************************************************
  * Function:  stm32_dumpgpio
  *
  * Description:
@@ -236,14 +260,16 @@ EXTERN int stm32_dumpgpio(uint32_t pinset, const char *msg);
 
 
 /************************************************************************************
- * Function:  stm32_gpio_remap
+ * Function:  stm32_gpioinit
  *
  * Description:
- *   Based on configuration within the .config file, remap positions of alternative
- *   functions. Typically called from stm32_start().
+ *   Based on configuration within the .config file, it does:
+ *    - Remaps positions of alternative functions. 
+ * 
+ * Typically called from stm32_start().
  ************************************************************************************/
 
-EXTERN void stm32_gpio_remap(void);
+EXTERN void stm32_gpioinit(void);
 
 #undef EXTERN
 #if defined(__cplusplus)
diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.c b/nuttx/arch/arm/src/stm32/stm32_spi.c
index 1317ef094..b4ba555af 100755
--- a/nuttx/arch/arm/src/stm32/stm32_spi.c
+++ b/nuttx/arch/arm/src/stm32/stm32_spi.c
@@ -1289,9 +1289,9 @@ static void spi_portinitialize(FAR struct stm32_spidev_s *priv)
 FAR struct spi_dev_s *up_spiinitialize(int port)
 {
   FAR struct stm32_spidev_s *priv = NULL;
-  irqstate_t flags;
 
-  flags = irqsave();
+  irqstate_t flags = irqsave();
+  
 #ifdef CONFIG_STM32_SPI1
   if (port == 1)
     {
@@ -1301,16 +1301,6 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_spi1dev;
 
-      /* Handle pin mapping */
-
-      mapr = getreg32(STM32_AFIO_MAPR);
-#ifdef CONFIG_STM32_SPI1_REMAP
-      mapr |= AFIO_MAPR_SPI1_REMAP;
-#else
-      mapr &= ~AFIO_MAPR_SPI1_REMAP;
-#endif
-      putreg32(mapr, STM32_AFIO_MAPR);
-
       /* Configure SPI1 pins: SCK, MISO, and MOSI */
 
       stm32_configgpio(GPIO_SPI1_SCK);
@@ -1330,6 +1320,12 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_spi2dev;
 
+      /* Configure SPI2 pins: SCK, MISO, and MOSI */
+
+      stm32_configgpio(GPIO_SPI2_SCK);
+      stm32_configgpio(GPIO_SPI2_MISO);
+      stm32_configgpio(GPIO_SPI2_MOSI);
+
       /* Set up default configuration: Master, 8-bit, etc. */
 
       spi_portinitialize(priv);
@@ -1343,12 +1339,6 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_spi3dev;
 
-      /* Handle pin mapping */
-
-#ifdef CONFIG_STM32_SPI3_REMAP
-#  error "Available only in connectivity devices"
-#endif
-
       /* Configure SPI3 pins: SCK, MISO, and MOSI */
 
       stm32_configgpio(GPIO_SPI3_SCK);
diff --git a/nuttx/arch/arm/src/stm32/stm32_start.c b/nuttx/arch/arm/src/stm32/stm32_start.c
index ca47f540a..ce7aeb53a 100644
--- a/nuttx/arch/arm/src/stm32/stm32_start.c
+++ b/nuttx/arch/arm/src/stm32/stm32_start.c
@@ -85,7 +85,7 @@ void __start(void)
 
   stm32_clockconfig();
   stm32_lowsetup();
-  stm32_gpio_remap();
+  stm32_gpioinit();
   showprogress('A');
 
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be