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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-05-22 18:12:54 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-05-22 18:12:54 -0600 |
| commit | 371d564efd88053842c29526aefd8ae4ea7436b4 (patch) | |
| tree | aeb72779dbdd3193a4030fe743db87c5046615d1 /nuttx/arch/arm/src | |
| parent | 8b20e839a7d43a8228077f27b19df02a0b82aee9 (diff) | |
| download | px4-nuttx-371d564efd88053842c29526aefd8ae4ea7436b4.tar.gz px4-nuttx-371d564efd88053842c29526aefd8ae4ea7436b4.tar.bz2 px4-nuttx-371d564efd88053842c29526aefd8ae4ea7436b4.zip | |
Beginning of a segment LCD driver for the STM32L-Discovery
Diffstat (limited to 'nuttx/arch/arm/src')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_lcd.h | 31 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h | 5 |
2 files changed, 21 insertions, 15 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_lcd.h b/nuttx/arch/arm/src/stm32/chip/stm32_lcd.h index 9f342c55b..d79348bcf 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_lcd.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_lcd.h @@ -58,9 +58,9 @@ #define STM32_LCD_SR_OFFSET 0x0008 /* LCD status register */ #define STM32_LCD_CLR_OFFSET 0x000c /* LCD clear register */ -#define STM32_LCD_RAM_OFFSET(n) (0x0014+((n) << 3)) /* LCD display memory, COMn */ -#define STM32_LCD_RAML_OFFSET(n) (0x0014+((n) << 3)) /* LCD display memory, COMn, S00-S31 */ -#define STM32_LCD_RAMH_OFFSET(n) (0x0018+((n) << 3)) /* LCD display memory, COMn, S32-S39 */ +#define STM32_LCD_RAM_OFFSET(n) (0x0014 + ((n) << 3)) /* LCD display memory, COMn */ +#define STM32_LCD_RAML_OFFSET(n) (0x0014 + ((n) << 3)) /* LCD display memory, COMn, S00-S31 */ +#define STM32_LCD_RAMH_OFFSET(n) (0x0018 + ((n) << 3)) /* LCD display memory, COMn, S32-S39 */ #define STM32_LCD_RAM0L_OFFSET 0x0014 /* LCD display memory, COM0, S00-S31 */ #define STM32_LCD_RAM0H_OFFSET 0x0018 /* LCD display memory, COM0, S32-S39 */ @@ -111,20 +111,21 @@ /* LCD control register */ -#define LCD_CR_LCDEN (1 << 0) /* Bit 0: LCD controller enable */ -#define LCD_CR_VSEL (1 << 1) /* Bit 1: Voltage source selection */ -#define LCD_CR_DUTY_SHIFT (2) /* Bits 2-4: Duty selection */ +#define LCD_CR_LCDEN (1 << 0) /* Bit 0: LCD controller enable */ +#define LCD_CR_VSEL (1 << 1) /* Bit 1: Voltage source selection */ +#define LCD_CR_DUTY_SHIFT (2) /* Bits 2-4: Duty selection */ #define LCD_CR_DUTY_MASK (7 << LCD_CR_DUTY_SHIFT) -# define LCD_CR_DUTY_STATIC (7 << LCD_CR_DUTY_SHIFT) /* 000: Static duty */ -# define LCD_CR_DUTY_1TO2 (7 << LCD_CR_DUTY_SHIFT) /* 001: 1/2 duty */ -# define LCD_CR_DUTY_1TO3 (7 << LCD_CR_DUTY_SHIFT) /* 010: 1/3 duty */ -# define LCD_CR_DUTY_1TO4 (7 << LCD_CR_DUTY_SHIFT) /* 011: 1/4 duty */ -# define LCD_CR_DUTY_1TO8 (7 << LCD_CR_DUTY_SHIFT) /* 100: 1/8 duty */ +# define LCD_CR_DUTY_STATIC (0 << LCD_CR_DUTY_SHIFT) /* 000: Static duty */ +# define LCD_CR_DUTY_1TO2 (1 << LCD_CR_DUTY_SHIFT) /* 001: 1/2 duty */ +# define LCD_CR_DUTY_1TO3 (2 << LCD_CR_DUTY_SHIFT) /* 010: 1/3 duty */ +# define LCD_CR_DUTY_1TO4 (3 << LCD_CR_DUTY_SHIFT) /* 011: 1/4 duty */ +# define LCD_CR_DUTY_1TO8 (4 << LCD_CR_DUTY_SHIFT) /* 100: 1/8 duty */ #define LCD_CR_BIAS_SHIFT (5) /* Bits 5-6: Bias selector */ #define LCD_CR_BIAS_MASK (3 << LCD_CR_BIAS_SHIFT) -# define LCD_CR_BIAS_1TO4 (3 << LCD_CR_BIAS_SHIFT) /* 00: Bias 1/4 */ -# define LCD_CR_BIAS_1TO2 (3 << LCD_CR_BIAS_SHIFT) /* 01: Bias 1/2 */ -# define LCD_CR_BIAS_1TO3 (3 << LCD_CR_BIAS_SHIFT) /* 10: Bias 1/3 */ +# define LCD_CR_BIAS_1TO4 (0 << LCD_CR_BIAS_SHIFT) /* 00: Bias 1/4 */ +# define LCD_CR_BIAS_1TO2 (1 << LCD_CR_BIAS_SHIFT) /* 01: Bias 1/2 */ +# define LCD_CR_BIAS_1TO3 (2 << LCD_CR_BIAS_SHIFT) /* 10: Bias 1/3 */ +#define LCD_CR_MUX_SEG (1 << 7) /* Bit 7: Mux segment enable /* Bits 8-31 Reserved */ /* LCD frame control register */ @@ -138,7 +139,7 @@ # define LCD_FCR_PON(n) ((n) << LCD_FCR_PON_SHIFT) /* n=0-7 */ #define LCD_FCR_DEAD_SHIFT (7) /* Bits 7-9: Dead time duration */ #define LCD_FCR_DEAD_MASK (7 << LCD_FCR_DEAD_SHIFT) -# define LCD_FCR_DEAD_NONE (7 << LCD_FCR_DEAD_SHIFT) +# define LCD_FCR_DEAD_NONE (0 << LCD_FCR_DEAD_SHIFT) # define LCD_FCR_DEAD(n) ((n) << LCD_FCR_DEAD_SHIFT) /* n=1..7 */ #define LCD_FCR_CC_SHIFT (10) /* Bits 10-12: Contrast control */ #define LCD_FCR_CC_MASK (7 << LCD_FCR_CC_SHIFT) diff --git a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h index e437c68d7..cb37a16f6 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h @@ -65,6 +65,10 @@ #define STM32_OPTION_BASE 0x1ff80000 /* 0x1fffc000-0x1ff8001f: Option bytes */ /* 0x1ff80020-0x1fffffff: Reserved */ +/* SRAM Base Addresses **************************************************************/ + +#define STM32_SRAMBB_BASE 0x22000000 /* SRAM bit-band base */ + /* Peripheral Base Addresses ********************************************************/ #define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007c03: APB1 */ @@ -73,6 +77,7 @@ /* 0x40013c00-0x4001ffff: Reserved */ #define STM32_AHB_BASE 0x40020000 /* 0x40020000-0xa0000fff: AHB */ /* 0xa0001000-0x4fffffff: Reserved */ +#define STM32_PERIPHBB_BASE 0x42000000 /* Peripheral bit-band base */ /* APB1 Base Addresses **************************************************************/ |