Add support for STM32F100x value line. Contributed by Mike Smith. Still missing a file

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4955 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 155 insertions, 72 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h
index 4c3c77c20..cc3ee1f96 100644
--- a/nuttx/arch/arm/src/stm32/chip.h
+++ b/nuttx/arch/arm/src/stm32/chip.h
@@ -49,7 +49,9 @@
 /* Include the chip pin configuration file */
 
 #if defined(CONFIG_STM32_STM32F10XX)
-#  if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
+#  if defined(CONFIG_STM32_VALUELINE)
+#    include "chip/stm32f100_pinmap.h"
+#  elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6) 
 #    include "chip/stm32f103ze_pinmap.h"
 #  elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
 #    include "chip/stm32f103re_pinmap.h"
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
index 21d4648fa..31544c99f 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
@@ -52,6 +52,9 @@
 #define STM32_RCC_APB1ENR_OFFSET    0x001c  /* APB1 Peripheral Clock enable register */
 #define STM32_RCC_BDCR_OFFSET       0x0020  /* Backup domain control register */
 #define STM32_RCC_CSR_OFFSET        0x0024  /* Control/status register */
+#ifdef CONFIG_STM32_VALUELINE
+#  define STM32_RCC_CFGR2_OFFSET    0x002c  /* Clock configuration register 2 */
+#endif
 
 /* Register Addresses ***************************************************************/
 
@@ -65,6 +68,9 @@
 #define STM32_RCC_APB1ENR           (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
 #define STM32_RCC_BDCR              (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
 #define STM32_RCC_CSR               (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
+#ifdef CONFIG_STM32_VALUELINE
+#  define STM32_RCC_CFGR2           (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET)
+#endif
 
 /* Register Bitfield Definitions ****************************************************/
 
@@ -295,5 +301,28 @@
 #define RCC_CSR_WWDGRSTF            (1 << 30) /* Bit 30: Window watchdog reset flag */
 #define RCC_CSR_LPWRRSTF            (1 << 31) /* Bit 31: Low-Power reset flag */
 
+#ifdef CONFIG_STM32_VALUELINE
+
+/* Clock configuration register 2 */
+
+#  define RCC_CFGR2_PREDIV1d1       0  /* HSE input not divided */
+#  define RCC_CFGR2_PREDIV1d2       1  /* HSE input divided by 2 */
+#  define RCC_CFGR2_PREDIV1d3       2  /* HSE input divided by 3 */
+#  define RCC_CFGR2_PREDIV1d4       3  /* HSE input divided by 4 */
+#  define RCC_CFGR2_PREDIV1d5       4  /* HSE input divided by 5 */
+#  define RCC_CFGR2_PREDIV1d6       5  /* HSE input divided by 6 */
+#  define RCC_CFGR2_PREDIV1d7       6  /* HSE input divided by 7 */
+#  define RCC_CFGR2_PREDIV1d8       7  /* HSE input divided by 8 */
+#  define RCC_CFGR2_PREDIV1d9       8  /* HSE input divided by 9 */
+#  define RCC_CFGR2_PREDIV1d10      9  /* HSE input divided by 10 */
+#  define RCC_CFGR2_PREDIV1d11      10 /* HSE input divided by 11 */
+#  define RCC_CFGR2_PREDIV1d12      11 /* HSE input divided by 12 */
+#  define RCC_CFGR2_PREDIV1d13      12 /* HSE input divided by 13 */
+#  define RCC_CFGR2_PREDIV1d14      13 /* HSE input divided by 14 */
+#  define RCC_CFGR2_PREDIV1d15      14 /* HSE input divided by 15 */
+#  define RCC_CFGR2_PREDIV1d16      15 /* HSE input divided by 16 */
+
+#endif
+
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RCC_H */
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
index 53ce4996e..d18c7e789 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
@@ -43,7 +43,23 @@
  * the interrupt vectors and handlers in their final form.
  */
 
-#ifdef CONFIG_STM32_CONNECTIVITY_LINE
+#if defined(CONFIG_STM32_VALUELINE)
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 60 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 60
+
+#else
+#  error This target requires CONFIG_ARMV7M_CMNVECTOR
+#endif /* CONFIG_ARMV7M_CMNVECTOR */
+
+#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
 
 /* If the common ARMv7-M vector handling is used, then all it needs is the following
  * definition that provides the number of supported vectors.
@@ -119,7 +135,7 @@ VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE)         /* Vector 16+66: CAN2 SCE inter
 VECTOR(stm32_otgfs, STM32_IRQ_OTGFS)             /* Vector 16+67: USB On The Go FS global interrupt */
 
 #endif /* CONFIG_ARMV7M_CMNVECTOR */
-#else /* CONFIG_STM32_CONNECTIVITY_LINE */
+#else /* CONFIG_STM32_CONNECTIVITYLINE */
 
 /* If the common ARMv7-M vector handling is used, then all it needs is the following
  * definition that provides the number of supported vectors.
@@ -195,4 +211,4 @@ VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3)         /* Vector 16+58: DMA2 Channel 3
 VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45)       /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
 
 #endif /* CONFIG_ARMV7M_CMNVECTOR */
-#endif /* CONFIG_STM32_CONNECTIVITY_LINE */
+#endif /* CONFIG_STM32_CONNECTIVITYLINE */
diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
index f7f6c20b7..f9e3cb7a6 100644
--- a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -415,92 +415,128 @@ static inline void rcc_enableapb2(void)
 static inline void stm32_stdclockconfig(void)
 {
   uint32_t regval;
-  volatile int32_t timeout;
 
-  /* Enable External High-Speed Clock (HSE) */
- 
-  regval  = getreg32(STM32_RCC_CR);
-  regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
-  regval |= RCC_CR_HSEON;           /* Enable HSE */
-  putreg32(regval, STM32_RCC_CR);
-   
-  /* Wait until the HSE is ready (or until a timeout elapsed) */
+  /* If the PLL is using the HSE, or the HSE is the system clock */
+
+#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
 
-  for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
   {
-    /* Check if the HSERDY flag is the set in the CR */
+    volatile int32_t timeout;
+
+    /* Enable External High-Speed Clock (HSE) */
+   
+    regval  = getreg32(STM32_RCC_CR);
+    regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
+    regval |= RCC_CR_HSEON;           /* Enable HSE */
+    putreg32(regval, STM32_RCC_CR);
+
+    /* Wait until the HSE is ready (or until a timeout elapsed) */
+
+    for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
+      {
+        /* Check if the HSERDY flag is the set in the CR */
+
+        if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
+          {
+            /* If so, then break-out with timeout > 0 */
+
+            break;
+          }
+      }
 
-    if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
+    if (timeout == 0)
       {
-        /* If so, then break-out with timeout > 0 */
+        /* In the case of a timeout starting the HSE, we really don't have a
+         * strategy.  This is almost always a hardware failure or misconfiguration.
+         */
 
-        break;
+        return;
       }
   }
 
-  /* Check for a timeout.  If this timeout occurs, then we are hosed.  We
-   * have no real back-up plan, although the following logic makes it look
-   * as though we do.
-   */
+  /* If this is a value-line part and we are using the HSE as the PLL */
 
-  if (timeout > 0)
-    {
-      /* Enable FLASH prefetch buffer and 2 wait states */
+# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
 
-      regval  = getreg32(STM32_FLASH_ACR);
-      regval &= ~FLASH_ACR_LATENCY_MASK;
-      regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
-      putreg32(regval, STM32_FLASH_ACR);
+# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
+#  error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
+# endif
 
-      /* Set the HCLK source/divider */
- 
-      regval = getreg32(STM32_RCC_CFGR);
-      regval &= ~RCC_CFGR_HPRE_MASK;
-      regval |= STM32_RCC_CFGR_HPRE;
-      putreg32(regval, STM32_RCC_CFGR);
+    /* Set the HSE prescaler */
 
-      /* Set the PCLK2 divider */
+    regval = STM32_CFGR2_PREDIV1;
+    putreg32(regval, STM32_RCC_CFGR2);
 
-      regval = getreg32(STM32_RCC_CFGR);
-      regval &= ~RCC_CFGR_PPRE2_MASK;
-      regval |= STM32_RCC_CFGR_PPRE2;
-      putreg32(regval, STM32_RCC_CFGR);
-  
-      /* Set the PCLK1 divider */
+# endif
+#endif
 
-      regval = getreg32(STM32_RCC_CFGR);
-      regval &= ~RCC_CFGR_PPRE1_MASK;
-      regval |= STM32_RCC_CFGR_PPRE1;
-      putreg32(regval, STM32_RCC_CFGR);
- 
-      /* Set the PLL divider and multipler */
+    /* Value-line devices don't implement flash prefetch/waitstates */
 
-      regval = getreg32(STM32_RCC_CFGR);
-      regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
-      regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
-      putreg32(regval, STM32_RCC_CFGR);
- 
-      /* Enable the PLL */
+#ifndef CONFIG_STM32_VALUELINE
 
-      regval = getreg32(STM32_RCC_CR);
-      regval |= RCC_CR_PLLON;
-      putreg32(regval, STM32_RCC_CR);
- 
-      /* Wait until the PLL is ready */
-  
-      while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
- 
-      /* Select the system clock source (probably the PLL) */
- 
-      regval  = getreg32(STM32_RCC_CFGR);
-      regval &= ~RCC_CFGR_SW_MASK;
-      regval |= STM32_SYSCLK_SW;
-      putreg32(regval, STM32_RCC_CFGR);
+    /* Enable FLASH prefetch buffer and 2 wait states */
 
-      /* Wait until the selected source is used as the system clock source */
-  
-      while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
-  }
+    regval  = getreg32(STM32_FLASH_ACR);
+    regval &= ~FLASH_ACR_LATENCY_MASK;
+    regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
+    putreg32(regval, STM32_FLASH_ACR);
+
+#endif
+
+    /* Set the HCLK source/divider */
+
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_HPRE_MASK;
+    regval |= STM32_RCC_CFGR_HPRE;
+    putreg32(regval, STM32_RCC_CFGR);
+
+    /* Set the PCLK2 divider */
+
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_PPRE2_MASK;
+    regval |= STM32_RCC_CFGR_PPRE2;
+    putreg32(regval, STM32_RCC_CFGR);
+
+    /* Set the PCLK1 divider */
+
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_PPRE1_MASK;
+    regval |= STM32_RCC_CFGR_PPRE1;
+    putreg32(regval, STM32_RCC_CFGR);
+
+    /* If we are using the PLL, configure and start it */
+
+#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
+
+    /* Set the PLL divider and multipler */
+
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
+    regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
+    putreg32(regval, STM32_RCC_CFGR);
+
+    /* Enable the PLL */
+
+    regval = getreg32(STM32_RCC_CR);
+    regval |= RCC_CR_PLLON;
+    putreg32(regval, STM32_RCC_CR);
+
+    /* Wait until the PLL is ready */
+
+    while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
+
+#endif
+
+    /* Select the system clock source (probably the PLL) */
+
+    regval  = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_SW_MASK;
+    regval |= STM32_SYSCLK_SW;
+    putreg32(regval, STM32_RCC_CFGR);
+
+    /* Wait until the selected source is used as the system clock source */
+
+    while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
 }
 #endif