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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-10 21:47:42 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-10 21:47:42 +0000 |
commit | 9914f20a1ae77ceb469301105ed4e3c16698a72c (patch) | |
tree | c8b31a4c22428db12eacde24d23a53f53c41106a /nuttx/arch/arm/src | |
parent | f8731df8137c569696cddec635ce82f178f22bbe (diff) | |
download | px4-nuttx-9914f20a1ae77ceb469301105ed4e3c16698a72c.tar.gz px4-nuttx-9914f20a1ae77ceb469301105ed4e3c16698a72c.tar.bz2 px4-nuttx-9914f20a1ae77ceb469301105ed4e3c16698a72c.zip |
Add Ethernet descriptor definitions and initialization
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4158 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src')
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_eth.h | 169 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_eth.c | 222 |
2 files changed, 382 insertions, 9 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h index 991695a09..992c59a3f 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h @@ -349,6 +349,7 @@ #define ETH_MACIMR_PMTIM (1 << 3) /* Bit 3: PMT interrupt mask */ #define ETH_MACIMR_TSTIM (1 << 9) /* Bit 9: Time stamp trigger interrupt mask */ +#define ETH_MACIMR_ALLINTS (ETH_MACIMR_PMTIM|ETH_MACIMR_TSTIM) /* Ethernet MAC address 0 high register */ @@ -643,12 +644,177 @@ /* Ethernet DMA current host transmit buffer address register (32-bit address) */ /* Ethernet DMA current host receive buffer address register (32-bit address) */ +/* DMA Descriptors **********************************************************************************/ +/* TDES0: Transmit descriptor Word0 */ + +#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */ +#define ETH_TDES0_UF (1 << 1) /* Bit 1: Underflow error */ +#define ETH_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */ +#define ETH_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */ +#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT) +#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */ +#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */ +#define ETH_TDES0_LCO (1 << 9) /* Bit 9: Late collision */ +#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */ +#define ETH_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */ +#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */ +#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */ +#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */ +#define ETH_TDES0_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_TDES0_IHE (1 << 16) /* Bit 16: IP header error */ +#define ETH_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */ +#define ETH_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */ +#define ETH_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */ +#define ETH_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */ +#define ETH_TDES0_CIC_MASK (3 << ETH_TDES0_CIC_SHIFT) +# define ETH_TDES0_CIC_DISABLED (0 << ETH_TDES0_CIC_SHIFT) /* Checksum disabled */ +# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */ +# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */ +# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */ +#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */ +#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */ +#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */ +#define ETH_TDES0_FS (1 << 28) /* Bit 28: First segment */ +#define ETH_TDES0_LS (1 << 29) /* Bit 29: Last segment */ +#define ETH_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */ +#define ETH_TDES0_OWN (1 << 31) /* Bit 31: Own bit */ + +/* TDES1: Transmit descriptor Word1 */ + +#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */ +#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT) +#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */ +#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT) + +/* TDES2: Transmit descriptor Word2 (32-bit address) */ +/* TDES3: Transmit descriptor Word3 (32-bit address) */ +/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */ +/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */ + +/* RDES0: Receive descriptor Word0 */ + +#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ +#define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ +#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ +#define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */ +#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */ +#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */ +#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */ +#define ETH_RDES0_LCO (1 << 6) /* Bit 6: Late collision */ +#define ETH_RDES0_TSV (1 << 7) /* Bit 7: Time stamp valid */ +#define ETH_RDES0_IPHCE (1 << 7) /* Bit 7: IPv header checksum error */ +#define ETH_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */ +#define ETH_RDES0_FS (1 << 9) /* Bit 9: First descriptor */ +#define ETH_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */ +#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */ +#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */ +#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */ +#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */ +#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */ +#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT) +#define ETH_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */ +#define ETH_RDES0_OWN (1 << 31) /* Bit 31: Own bit */ + +/* RDES1: Receive descriptor Word1 */ + +#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */ +#define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT) +#define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */ +#define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */ +#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */ +#define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */ +#define ETH_RDES1_RBS2_MASK (0x1fff << ETH_RDES1_RBS2_SHIFT) + +/* RDES2: Receive descriptor Word2 (32-bit address) */ +/* RDES3: Receive descriptor Word3 (32-bit address) */ + +/* RDES4: Receive descriptor Word4 */ + +#define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */ +#define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */ +#define ETH_RDES4_PMT_SHIFT (8) /* Bits 8-11: PTP message type */ +#define ETH_RDES4_PMT_MASK (15 << ETH_RDES4_PMT_SHIFT) +# define ETH_RDES4_PMT_NONE (0 << ETH_RDES4_PMT_SHIFT) /* No PTP message received */ +# define ETH_RDES4_PMT_SYNC (1 << ETH_RDES4_PMT_SHIFT) /* SYNC (all clock types) */ +# define ETH_RDES4_PMT_FOLLOWUP (2 << ETH_RDES4_PMT_SHIFT) /* Follow_Up (all clock types) */ +# define ETH_RDES4_PMT_DELAYREQ (3 << ETH_RDES4_PMT_SHIFT) /* Delay_Req (all clock types) */ +# define ETH_RDES4_PMT_DELAYRESP (4 << ETH_RDES4_PMT_SHIFT) /* Delay_Resp (all clock types) */ +# define ETH_RDES4_PMT_PDELREQAM (5 << ETH_RDES4_PMT_SHIFT) /* 0101: Pdelay_Req (in peer-to-peer + * transparent clock) or Announce (in + * ordinary or boundary clock) */ +# define ETH_RDES4_PMT_PDELREQMM (6 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp (in peer-to-peer + * transparent clock) or Management (in + * ordinary or boundary clock) */ +# define ETH_RDES4_PMT_PDELREQFUS (7 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp_Follow_Up (in + * peer-to-peer transparent clock) or + * Signaling (for ordinary or boundary + * clock) */ +#define ETH_RDES4_IPV6PR (1 << 7) /* Bit 7: IPv6 packet received */ +#define ETH_RDES4_IPV4PR (1 << 6) /* Bit 6: IPv4 packet received */ +#define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */ +#define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ +#define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ +#define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */ +#define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT) +# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ +# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ +# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ + +/* RDES5: Receive descriptor Word5 - Reserved */ +/* RDES6: Receive descriptor Word6 (32-bit time stamp) */ +/* RDES7: Receive descriptor Word7 (32-bit time stamp) */ + /**************************************************************************************************** - * Public Functions + * Public Types ****************************************************************************************************/ #ifndef __ASSEMBLY__ +/* Ethernet TX DMA Descriptor */ + +struct eth_txdesc_s +{ + /* Normal DMA descriptor words */ + + volatile uint32_t tdes0; /* Status */ + volatile uint32_t tdes1; /* Control and buffer1/2 lengths */ + volatile uint32_t tdes2; /* Buffer1 address pointer */ + volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */ + + /* Enhanced DMA descriptor words with time stamp */ + +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC + volatile uint32_t tdes4; /* Reserved */ + volatile uint32_t tdes5; /* Reserved */ + volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ + volatile uint32_t tdes7; /* Time Stamp High value for transmit and receive */ +#endif +}; + +/* Ethernet RX DMA Descriptor */ + +struct eth_rxdesc_s +{ + volatile uint32_t rdes0; /* Status */ + volatile uint32_t rdes1; /* Control and buffer1/2 lengths */ + volatile uint32_t rdes2; /* Buffer1 address pointer */ + volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */ + + /* Enhanced DMA descriptor words with time stamp and PTP support */ + +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC + volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ + volatile uint32_t rdes5; /* Reserved */ + volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ + volatile uint32_t rdes7; /* Time Stamp High value for transmit and receive */ +#endif +}; + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" @@ -657,7 +823,6 @@ extern "C" { #define EXTERN extern #endif - #endif /* __ASSEMBLY__ */ #endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.c b/nuttx/arch/arm/src/stm32/stm32_eth.c index d4c833f40..79d0fd9dd 100755 --- a/nuttx/arch/arm/src/stm32/stm32_eth.c +++ b/nuttx/arch/arm/src/stm32/stm32_eth.c @@ -131,12 +131,13 @@ # warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif -/* This driver always uses enhanced descriptors. However, this would not be - * the cased if support is added for stamping and/or IPv4 checksum offload +/* This driver does not use enhanced descriptors. Enhanced descriptors must + * be used, however, if time stamping or and/or IPv4 checksum offload is + * supported. */ -#define CONFIG_STM32_ETH_ENHANCEDDESC 1 -#undef CONFIG_STM32_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_ENHANCEDDESC +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Ethernet buffer sizes and numbers */ @@ -462,6 +463,13 @@ * Private Types ****************************************************************************/ +struct eth_rxframe_info_s +{ + volatile struct stm2_ethdesc_s *rxfirst; /* First Segment Rx Desc */ + volatile struct stm2_ethdesc_s *rxlast; /* Last Segment Rx Desc */ + volatile uint32_t segcount; /* Segment count */ +}; + /* The stm32_ethmac_s encapsulates all state information for a single hardware * interface */ @@ -477,6 +485,26 @@ struct stm32_ethmac_s /* This holds the information visible to uIP/NuttX */ struct uip_driver_s dev; /* Interface understood by uIP */ + + /* Used to track transmit and receive descriptors */ + + volatile struct eth_txdesc_s *txdesc; + volatile struct eth_rxdesc_s *rxdesc; + + /* Frame info */ + + struct eth_rxframe_info_s rxframe; + volatile struct eth_rxframe_info_s *rxframeinfo; + + /* Descriptor allocations */ + + struct eth_rxdesc_s rxtable[CONFIG_STM32_ETH_RXNBUFFERS]; + struct eth_txdesc_s txtable[CONFIG_STM32_ETH_TXNBUFFERS]; + + /* Buffer allocations */ + + uint8_t rxbuffer[CONFIG_STM32_ETH_RXNBUFFERS*CONFIG_STM32_ETH_RXBUFSIZE]; + uint8_t txbuffer[CONFIG_STM32_ETH_TXNBUFFERS*CONFIG_STM32_ETH_TXBUFSIZE]; }; /**************************************************************************** @@ -515,6 +543,11 @@ static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac); static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); #endif +/* Descriptor Initialization */ + +static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv); +static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv); + /* PHY Initialization */ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value); @@ -526,6 +559,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv); static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv); static void stm32_ethreset(FAR struct stm32_ethmac_s *priv); static int stm32_macconfig(FAR struct stm32_ethmac_s *priv); +static int stm32_macenable(FAR struct stm32_ethmac_s *priv); static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv); /**************************************************************************** @@ -1091,6 +1125,136 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) #endif /**************************************************************************** + * Function: stm32_txdescinit + * + * Description: + * Initializes the DMA TX descriptors in chain mode. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv) +{ + struct eth_txdesc_s *txdesc; + int i; + + /* Set the priv->txdesc pointer with the first descriptor in the table */ + + priv->txdesc = priv->txtable; + + /* Initialize each TX descriptor */ + + for (i = 0; i < CONFIG_STM32_ETH_TXNBUFFERS; i++) + { + txdesc = &priv->txtable[i]; + + /* Set Second Address Chained bit */ + + txdesc->tdes0 = ETH_TDES0_TCH; + + /* Set Buffer1 address pointer */ + + txdesc->tdes2 = (uint32_t)(&priv->txbuffer[i*CONFIG_STM32_ETH_TXBUFSIZE]); + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + + if( i < (CONFIG_STM32_ETH_TXNBUFFERS-1)) + { + /* Set next descriptor address register with next descriptor base + * address + */ + + txdesc->tdes3 = (uint32_t)&priv->txtable[i+1]; + } + else + { + /* For last descriptor, set next descriptor address register equal + * to the first descriptor base address + */ + + txdesc->tdes3 = (uint32_t)priv->txtable; + } + } +} + +/**************************************************************************** + * Function: stm32_rxdescinit + * + * Description: + * Initializes the DMA RX descriptors in chain mode. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv) +{ + struct eth_rxdesc_s *rxdesc; + int i; + + /* Set the priv->rxdesc pointer with the first one of the table list */ + + priv->rxdesc = priv->rxtable; + + /* Initialize each TX descriptor */ + + for (i = 0; i < CONFIG_STM32_ETH_RXNBUFFERS; i++) + { + rxdesc = &priv->rxtable[i]; + + /* Set Own bit of the Rx descriptor rdes0 */ + + rxdesc->rdes0 = ETH_RDES0_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + + rxdesc->rdes1 = ETH_RDES1_RCH | (uint32_t)CONFIG_STM32_ETH_RXBUFSIZE; + + /* Set Buffer1 address pointer */ + + rxdesc->rdes2 = (uint32_t)&priv->rxbuffer[i*CONFIG_STM32_ETH_RXBUFSIZE]; + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + + if( i < (CONFIG_STM32_ETH_RXNBUFFERS-1)) + { + /* Set next descriptor address register with next descriptor base + * address + */ + + rxdesc->rdes3 = (uint32_t)&priv->rxtable[i+1]; + } + else + { + /* For last descriptor, set next descriptor address register equal + * to the first descriptor base address + */ + + rxdesc->rdes3 = (uint32_t)priv->rxtable; + } + } + + /* Set Receive Descriptor List Address Register */ + + putreg32((uint32_t)priv->rxtable, STM32_ETH_DMARDLAR); + + priv->rxframeinfo = &priv->rxframe; +} + +/**************************************************************************** * Function: stm32_phyread * * Description: @@ -1590,6 +1754,31 @@ static int stm32_macconfig(FAR struct stm32_ethmac_s *priv) regval |= DMABMR_SET_MASK; putreg32(regval, STM32_ETH_DMABMR); + return OK; +} + +/**************************************************************************** + * Function: stm32_macenable + * + * Description: + * Enable normal MAC operation. + * + * Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_macenable(FAR struct stm32_ethmac_s *priv) +{ + /* Enable RX and TX */ +#warning "Missing Logic" + + /* Enable Ethernet DMA interrupts. * * The STM32 hardware supports two interrupts: (1) one dedicated to normal @@ -1599,8 +1788,11 @@ static int stm32_macconfig(FAR struct stm32_ethmac_s *priv) * The first Ethernet vector is reserved for interrupts generated by the * MAC and the DMA. The MAC provides PMT and time stamp trigger interrupts, * neither of which are used by this driver. - * - * Ethernet DMA supports two classes of interrupts: Normal interrupt + */ + + putreg32(ETH_MACIMR_ALLINTS, STM32_ETH_MACIMR); + + /* Ethernet DMA supports two classes of interrupts: Normal interrupt * summary (NIS) and Abnormal interrupt summary (AIS) with a variety * individual normal and abnormal interrupting events. Here only * the normal receive event is enabled (unless DEBUG is enabled). Transmit @@ -1649,7 +1841,23 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv) /* Initialize the MAC and DMA */ - return stm32_macconfig(priv); + ret = stm32_macconfig(priv); + if (ret < 0) + { + return ret; + } + + /* Initialize Tx Descriptors list: Chain Mode */ + + stm32_txdescinit(priv); + + /* Initialize Rx Descriptors list: Chain Mode */ + + stm32_rxdescinit(priv); + + /* Enable normal MAC operation */ + + return stm32_macenable(priv); } /**************************************************************************** |