Add support for RAMTRON NVRAM devices

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3347 42af7a65-404d-4744-a932-0658087f49c3

7 files changed, 221 insertions, 191 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h
index f916f1682..9d6ed8eb3 100755
--- a/nuttx/arch/arm/src/stm32/chip.h
+++ b/nuttx/arch/arm/src/stm32/chip.h
@@ -53,7 +53,7 @@
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
 #  define CONFIG_STM32_HIGHDENSITY       1   /* STM32F101x  and STM32F103x w/ 256/512 Kbytes */
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
-#  define STM32_NATIM                    1   /* One advanced timers TIM1 */
+#  define STM32_NATIM                    1   /* One advanced timer TIM1 */
 #  define STM32_NGTIM                    4   /* General timers TIM2,3,4,5 */
 #  define STM32 NBTIM                    0   /* No basic timers */
 #  define STM32_NDMA                     2   /* DMA1-2 */
@@ -73,19 +73,19 @@
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
 #  define CONFIG_STM32_HIGHDENSITY       1   /* STM32F101x  and STM32F103x w/ 256/512 Kbytes */
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
-#  define STM32_NATIM                    1   /* One advanced timers TIM1 */
+#  define STM32_NATIM                    2   /* Two advanced timers TIM1 and TIM8 */
 #  define STM32_NGTIM                    4   /* General timers TIM2,3,4,5 */
-#  define STM32 NBTIM                    0   /* No basic timers */
+#  define STM32 NBTIM                    2   /* Two basic timers TIM6 and TIM7 */
 #  define STM32_NDMA                     2   /* DMA1-2 */
-#  define STM32_NSPI                     2   /* SPI1-2 */
-#  define STM32_NUSART                   3   /* USART1-3 */
+#  define STM32_NSPI                     3   /* SPI1-3 */
+#  define STM32_NUSART                   5   /* USART1-5 */
 #  define STM32_NI2C                     2   /* I2C1-2 */
 #  define STM32_NCAN                     1   /* bxCAN1 */
 #  define STM32_NSDIO                    1   /* SDIO */
-#  define STM32_NGPIO                    112 /* GPIOA-G */
-#  define STM32_NADC                     1   /* ADC1 */
-#  define STM32_NDAC                     0   /* No DAC */
-#  define STM32_NCRC                     0   /* No CRC */
+#  define STM32_NGPIO                    51  /* GPIOA-D */
+#  define STM32_NADC                     2   /* ADC1-2 */
+#  define STM32_NDAC                     2   /* DAC1-2 */
+#  define STM32_NCRC                     1   /* CRC */
 #  define STM32_NTHERNET                 0   /* No ethernet */
 
 #elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c
index c789a5643..1b998d858 100755
--- a/nuttx/arch/arm/src/stm32/stm32_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c
@@ -210,7 +210,7 @@ static inline void rcc_enableapb1(void)
   regval |= RCC_APB1ENR_SPI2EN;
 #endif
   
-#if CONFIG_STM32_SPI4
+#if CONFIG_STM32_SPI3
   /* SPI 3 clock enable */
 
   regval |= RCC_APB1ENR_SPI3EN;
diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.c b/nuttx/arch/arm/src/stm32/stm32_sdio.c
index 90b4df6c9..895acbf37 100644
--- a/nuttx/arch/arm/src/stm32/stm32_sdio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_sdio.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32_sdio.c
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -1415,13 +1415,15 @@ static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
       clckr  = SDIO_CLKCR_MMCXFR;
       break;
 
-    case CLOCK_SD_TRANSFER_1BIT:  /* SD normal operation clocking (narrow 1-bit mode) */
-      clckr  = SDIO_CLCKR_SDXFR;
-      break;
-
     case CLOCK_SD_TRANSFER_4BIT:  /* SD normal operation clocking (wide 4-bit mode) */
+#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
       clckr  = SDIO_CLCKR_SDWIDEXFR;
       break;
+#endif
+
+    case CLOCK_SD_TRANSFER_1BIT:  /* SD normal operation clocking (narrow 1-bit mode) */
+      clckr  = SDIO_CLCKR_SDXFR;
+      break;
     };
 
   /* Set the new clock frequency and make sure that the clock is enabled or
@@ -2531,9 +2533,11 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
    */
 
   stm32_configgpio(GPIO_SDIO_D0);
+#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
   stm32_configgpio(GPIO_SDIO_D1);
   stm32_configgpio(GPIO_SDIO_D2);
   stm32_configgpio(GPIO_SDIO_D3);
+#endif
   stm32_configgpio(GPIO_SDIO_CK);
   stm32_configgpio(GPIO_SDIO_CMD);
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.c b/nuttx/arch/arm/src/stm32/stm32_spi.c
index d04b1aef0..1317ef094 100755
--- a/nuttx/arch/arm/src/stm32/stm32_spi.c
+++ b/nuttx/arch/arm/src/stm32/stm32_spi.c
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arm/arm/src/stm32/stm32_spi.c
  *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -760,6 +760,13 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   uint16_t setbits;
   uint32_t actual;
 
+  /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */
+
+  if (frequency > STM32_SPI_CLK_MAX)
+    {
+	  frequency = STM32_SPI_CLK_MAX;
+	}
+
   /* Has the frequency changed? */
 
 #ifndef CONFIG_SPI_OWNBUS
@@ -1286,7 +1293,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
   flags = irqsave();
 #ifdef CONFIG_STM32_SPI1
-  if (port == 0)
+  if (port == 1)
     {
       uint32_t mapr;
 
@@ -1317,7 +1324,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
   else
 #endif
 #ifdef CONFIG_STM32_SPI2
-  if (port == 1)
+  if (port == 2)
     {
       /* Select SPI2 */
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.h b/nuttx/arch/arm/src/stm32/stm32_spi.h
index 2d4721745..4ff4f1c42 100755
--- a/nuttx/arch/arm/src/stm32/stm32_spi.h
+++ b/nuttx/arch/arm/src/stm32/stm32_spi.h
@@ -1,158 +1,170 @@
-/************************************************************************************

- * arch/arm/src/stm32/stm32_spi.h

- *

- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.

- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

- *

- * Redistribution and use in source and binary forms, with or without

- * modification, are permitted provided that the following conditions

- * are met:

- *

- * 1. Redistributions of source code must retain the above copyright

- *    notice, this list of conditions and the following disclaimer.

- * 2. Redistributions in binary form must reproduce the above copyright

- *    notice, this list of conditions and the following disclaimer in

- *    the documentation and/or other materials provided with the

- *    distribution.

- * 3. Neither the name NuttX nor the names of its contributors may be

- *    used to endorse or promote products derived from this software

- *    without specific prior written permission.

- *

- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

- * POSSIBILITY OF SUCH DAMAGE.

- *

- ************************************************************************************/

-

-#ifndef __ARCH_ARM_STC_STM32_STM32_SPI_H

-#define __ARCH_ARM_STC_STM32_STM32_SPI_H

-

-/************************************************************************************

- * Included Files

- ************************************************************************************/

-

-#include <nuttx/config.h>

-

-#include "chip.h"

-

-/************************************************************************************

- * Pre-processor Definitions

- ************************************************************************************/

-

-/* Register Offsets *****************************************************************/

-

-#define STM32_SPI_CR1_OFFSET      0x0000  /* SPI Control Register 1 (16-bit) */

-#define STM32_SPI_CR2_OFFSET      0x0004  /* SPI control register 2 (16-bit) */

-#define STM32_SPI_SR_OFFSET       0x0008  /* SPI status register (16-bit) */

-#define STM32_SPI_DR_OFFSET       0x000c  /* SPI data register (16-bit) */

-#define STM32_SPI_CRCPR_OFFSET    0x0010  /* SPI CRC polynomial register (16-bit) */

-#define STM32_SPI_RXCRCR_OFFSET   0x0014  /* SPI Rx CRC register (16-bit) */

-#define STM32_SPI_TXCRCR_OFFSET   0x0018  /* SPI Tx CRC register (16-bit) */

-

-/* Register Addresses ***************************************************************/

-

-#if STM32_NSPI > 0

-#  define STM32_SPI1_CR1          (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)

-#  define STM32_SPI1_CR2          (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)

-#  define STM32_SPI1_SR           (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)

-#  define STM32_SPI1_DR           (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)

-#  define STM32_SPI1_CRCPR        (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)

-#  define STM32_SPI1_RXCRCR       (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)

-#  define STM32_SPI1_TXCRCR       (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)

-#endif

-

-#if STM32_NSPI > 1

-#  define STM32_SPI2_CR1          (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)

-#  define STM32_SPI2_CR2          (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)

-#  define STM32_SPI2_SR           (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)

-#  define STM32_SPI2_DR           (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)

-#  define STM32_SPI2_CRCPR        (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)

-#  define STM32_SPI2_RXCRCR       (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)

-#  define STM32_SPI2_TXCRCR       (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)

-#endif

-

-/* Register Bitfield Definitions ****************************************************/

-

-/* SPI Control Register 1 */

-

-#define SPI_CR1_CPHA              (1 << 0)  /* Bit 0: Clock Phase */

-#define SPI_CR1_CPOL              (1 << 1)  /* Bit 1: Clock Polarity */

-#define SPI_CR1_MSTR              (1 << 2)  /* Bit 2: Master Selection */

-#define SPI_CR1_BR_SHIFT          (3)       /* Bits 5:3 Baud Rate Control */

-#define SPI_CR1_BR_MASK           (7 << SPI_CR1_BR_SHIFT)

-#  define SPI_CR1_FPCLCKd2        (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */

-#  define SPI_CR1_FPCLCKd4        (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */

-#  define SPI_CR1_FPCLCKd8        (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */

-#  define SPI_CR1_FPCLCKd16       (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */

-#  define SPI_CR1_FPCLCKd32       (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */

-#  define SPI_CR1_FPCLCKd64       (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */

-#  define SPI_CR1_FPCLCKd128      (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */

-#  define SPI_CR1_FPCLCKd256      (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */

-#define SPI_CR1_SPE               (1 << 6)  /* Bit 6: SPI Enable */

-#define SPI_CR1_LSBFIRST          (1 << 7)  /* Bit 7: Frame Format */

-#define SPI_CR1_SSI               (1 << 8)  /* Bit 8: Internal slave select */

-#define SPI_CR1_SSM               (1 << 9)  /* Bit 9: Software slave management */

-#define SPI_CR1_RXONLY            (1 << 10) /* Bit 10: Receive only */

-#define SPI_CR1_DFF               (1 << 11) /* Bit 11: Data Frame Format */

-#define SPI_CR1_CRCNEXT           (1 << 12) /* Bit 12: Transmit CRC next */

-#define SPI_CR1_CRCEN             (1 << 13) /* Bit 13: Hardware CRC calculation enable */

-#define SPI_CR1_BIDIOE            (1 << 14) /* Bit 14: Output enable in bidirectional mode */

-#define SPI_CR1_BIDIMODE          (1 << 15) /* Bit 15: Bidirectional data mode enable */

-

-/* SPI Control Register 2 */

-

-#define SPI_CR2_RXDMAEN           (1 << 0)  /* Bit 0: Rx Buffer DMA Enable */

-#define SPI_CR2_TXDMAEN           (1 << 1)  /* Bit 1: Tx Buffer DMA Enable */

-#define SPI_CR2_SSOE              (1 << 2)  /* Bit 2: SS Output Enable */

-#define SPI_CR2_ERRIE             (1 << 5)  /* Bit 5: Error interrupt enable */

-#define SPI_CR2_RXNEIE            (1 << 6)  /* Bit 6: RX buffer not empty interrupt enable */

-#define SPI_CR2_TXEIE             (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */

-

-/* SPI status register */

-

-#define SPI_SR_RXNE               (1 << 0)  /* Bit 0: Receive buffer not empty */

-#define SPI_SR_TXE                (1 << 1)  /* Bit 1: Transmit buffer empty */

-#define SPI_SR_CRCERR             (1 << 4)  /* Bit 4: CRC error flag */

-#define SPI_SR_MODF               (1 << 5)  /* Bit 5: Mode fault */

-#define SPI_SR_OVR                (1 << 6)  /* Bit 6: Overrun flag */

-#define SPI_SR_BSY                (1 << 7)  /* Bit 7: Busy flag */

-

-/************************************************************************************

- * Public Types

- ************************************************************************************/

-

-/************************************************************************************

- * Public Data

- ************************************************************************************/

-

-#ifndef __ASSEMBLY__

-

-#undef EXTERN

-#if defined(__cplusplus)

-#define EXTERN extern "C"

-extern "C" {

-#else

-#define EXTERN extern

-#endif

-

-/************************************************************************************

- * Public Functions

- ************************************************************************************/

-

-#undef EXTERN

-#if defined(__cplusplus)

-}

-#endif

-

-#endif /* __ASSEMBLY__ */

-

-#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */

+/************************************************************************************
+ * arch/arm/src/stm32/stm32_spi.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_STC_STM32_STM32_SPI_H
+#define __ARCH_ARM_STC_STM32_STM32_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define STM32_SPI_CLK_MAX     18000000UL  /* Maximum allowed speed as per specifications for all SPIs */
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SPI_CR1_OFFSET      0x0000  /* SPI Control Register 1 (16-bit) */
+#define STM32_SPI_CR2_OFFSET      0x0004  /* SPI control register 2 (16-bit) */
+#define STM32_SPI_SR_OFFSET       0x0008  /* SPI status register (16-bit) */
+#define STM32_SPI_DR_OFFSET       0x000c  /* SPI data register (16-bit) */
+#define STM32_SPI_CRCPR_OFFSET    0x0010  /* SPI CRC polynomial register (16-bit) */
+#define STM32_SPI_RXCRCR_OFFSET   0x0014  /* SPI Rx CRC register (16-bit) */
+#define STM32_SPI_TXCRCR_OFFSET   0x0018  /* SPI Tx CRC register (16-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NSPI > 0
+#  define STM32_SPI1_CR1          (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI1_CR2          (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI1_SR           (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI1_DR           (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI1_CRCPR        (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI1_RXCRCR       (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI1_TXCRCR       (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32_NSPI > 1
+#  define STM32_SPI2_CR1          (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI2_CR2          (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI2_SR           (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI2_DR           (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI2_CRCPR        (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI2_RXCRCR       (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI2_TXCRCR       (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32_NSPI > 2
+#  define STM32_SPI3_CR1          (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI3_CR2          (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI3_SR           (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI3_DR           (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI3_CRCPR        (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI3_RXCRCR       (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI3_TXCRCR       (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* SPI Control Register 1 */
+
+#define SPI_CR1_CPHA              (1 << 0)  /* Bit 0: Clock Phase */
+#define SPI_CR1_CPOL              (1 << 1)  /* Bit 1: Clock Polarity */
+#define SPI_CR1_MSTR              (1 << 2)  /* Bit 2: Master Selection */
+#define SPI_CR1_BR_SHIFT          (3)       /* Bits 5:3 Baud Rate Control */
+#define SPI_CR1_BR_MASK           (7 << SPI_CR1_BR_SHIFT)
+#  define SPI_CR1_FPCLCKd2        (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
+#  define SPI_CR1_FPCLCKd4        (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
+#  define SPI_CR1_FPCLCKd8        (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
+#  define SPI_CR1_FPCLCKd16       (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
+#  define SPI_CR1_FPCLCKd32       (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
+#  define SPI_CR1_FPCLCKd64       (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
+#  define SPI_CR1_FPCLCKd128      (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
+#  define SPI_CR1_FPCLCKd256      (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
+#define SPI_CR1_SPE               (1 << 6)  /* Bit 6: SPI Enable */
+#define SPI_CR1_LSBFIRST          (1 << 7)  /* Bit 7: Frame Format */
+#define SPI_CR1_SSI               (1 << 8)  /* Bit 8: Internal slave select */
+#define SPI_CR1_SSM               (1 << 9)  /* Bit 9: Software slave management */
+#define SPI_CR1_RXONLY            (1 << 10) /* Bit 10: Receive only */
+#define SPI_CR1_DFF               (1 << 11) /* Bit 11: Data Frame Format */
+#define SPI_CR1_CRCNEXT           (1 << 12) /* Bit 12: Transmit CRC next */
+#define SPI_CR1_CRCEN             (1 << 13) /* Bit 13: Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE            (1 << 14) /* Bit 14: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE          (1 << 15) /* Bit 15: Bidirectional data mode enable */
+
+/* SPI Control Register 2 */
+
+#define SPI_CR2_RXDMAEN           (1 << 0)  /* Bit 0: Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN           (1 << 1)  /* Bit 1: Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE              (1 << 2)  /* Bit 2: SS Output Enable */
+#define SPI_CR2_ERRIE             (1 << 5)  /* Bit 5: Error interrupt enable */
+#define SPI_CR2_RXNEIE            (1 << 6)  /* Bit 6: RX buffer not empty interrupt enable */
+#define SPI_CR2_TXEIE             (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */
+
+/* SPI status register */
+
+#define SPI_SR_RXNE               (1 << 0)  /* Bit 0: Receive buffer not empty */
+#define SPI_SR_TXE                (1 << 1)  /* Bit 1: Transmit buffer empty */
+#define SPI_SR_CRCERR             (1 << 4)  /* Bit 4: CRC error flag */
+#define SPI_SR_MODF               (1 << 5)  /* Bit 5: Mode fault */
+#define SPI_SR_OVR                (1 << 6)  /* Bit 6: Overrun flag */
+#define SPI_SR_BSY                (1 << 7)  /* Bit 7: Busy flag */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */
diff --git a/nuttx/arch/arm/src/stm32/stm32f103re_pinmap.h b/nuttx/arch/arm/src/stm32/stm32f103re_pinmap.h
index fea301abb..c78f0bd9e 100644
--- a/nuttx/arch/arm/src/stm32/stm32f103re_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/stm32f103re_pinmap.h
@@ -284,17 +284,20 @@
 /* SDIO */
 
 #define GPIO_SDIO_D0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
-#define GPIO_SDIO_D1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
-#define GPIO_SDIO_D2      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
-#define GPIO_SDIO_D3      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
-#define GPIO_SDIO_D4      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_SDIO_D5      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
-#define GPIO_SDIO_D6      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
-#define GPIO_SDIO_D7      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+
+#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
+#  define GPIO_SDIO_D1    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
+#  define GPIO_SDIO_D2    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+#  define GPIO_SDIO_D3    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
+#  define GPIO_SDIO_D4    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#  define GPIO_SDIO_D5    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_SDIO_D6    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
+#  define GPIO_SDIO_D7    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+#endif
+
 #define GPIO_SDIO_CK      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
 #define GPIO_SDIO_CMD     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)
 
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h b/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h
index 93f7e9d84..6a635a855 100644
--- a/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h
@@ -356,13 +356,17 @@
 /* SDIO */
 
 #define GPIO_SDIO_D0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
-#define GPIO_SDIO_D1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
-#define GPIO_SDIO_D2      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
-#define GPIO_SDIO_D3      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
-#define GPIO_SDIO_D4      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_SDIO_D5      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
-#define GPIO_SDIO_D6      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
-#define GPIO_SDIO_D7      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+
+#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
+#  define GPIO_SDIO_D1    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
+#  define GPIO_SDIO_D2    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+#  define GPIO_SDIO_D3    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
+#  define GPIO_SDIO_D4    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#  define GPIO_SDIO_D5    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_SDIO_D6    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
+#  define GPIO_SDIO_D7    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+#endif
+
 #define GPIO_SDIO_CK      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
 #define GPIO_SDIO_CMD     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)