diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-05 16:41:20 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-05 16:41:20 +0000 |
| commit | b4739f795b424040fbd1644dca719d537918e575 (patch) | |
| tree | c15878eb7135a9de4b8650951cc1583dc7aa3679 /nuttx/arch/arm/src | |
| parent | a8fe687ddda5685208e42c503e17f3cade2aca46 (diff) | |
| download | px4-nuttx-b4739f795b424040fbd1644dca719d537918e575.tar.gz px4-nuttx-b4739f795b424040fbd1644dca719d537918e575.tar.bz2 px4-nuttx-b4739f795b424040fbd1644dca719d537918e575.zip | |
Fixes for STM32F40xxx port
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4135 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h | 24 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c | 4 |
3 files changed, 15 insertions, 15 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h index c1704fdf2..aa7353ed9 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h @@ -183,7 +183,7 @@ #define GPIO_MODER_ALT (2) /* Alternate mode */ #define GPIO_MODER_ANALOG (3) /* Analog mode */ -#define GPIO_MODER_SHIFT(n) ((n) << 2) +#define GPIO_MODER_SHIFT(n) ((n) << 1) #define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) #define GPIO_MODER0_SHIFT (0) @@ -231,7 +231,7 @@ #define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */ #define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */ -#define GPIO_OSPEED_SHIFT(n) ((n) << 2) +#define GPIO_OSPEED_SHIFT(n) ((n) << 1) #define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) #define GPIO_OSPEED0_SHIFT (0) @@ -273,7 +273,7 @@ #define GPIO_PUPDR_PULLUP (1) /* Pull-up */ #define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ -#define GPIO_PUPDR_SHIFT(n) ((n) << 2) +#define GPIO_PUPDR_SHIFT(n) ((n) << 1) #define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) #define GPIO_PUPDR0_SHIFT (0) @@ -329,7 +329,7 @@ /* GPIO alternate function low/high register */ -#define GPIO_AFR_SHIFT(n) ((n) << 4) +#define GPIO_AFR_SHIFT(n) ((n) << 2) #define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) #define GPIO_AFRL0_SHIFT (0) @@ -350,21 +350,21 @@ #define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) #define GPIO_AFRH8_SHIFT (0) -#define GPIO_AFRH8_MASK (15 << GPIO_AFRH0_SHIFT) +#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) #define GPIO_AFRH9_SHIFT (4) -#define GPIO_AFRH9_MASK (15 << GPIO_AFRH1_SHIFT) +#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) #define GPIO_AFRH10_SHIFT (8) -#define GPIO_AFRH10_MASK (15 << GPIO_AFRH2_SHIFT) +#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) #define GPIO_AFRH11_SHIFT (12) -#define GPIO_AFRH11_MASK (15 << GPIO_AFRH3_SHIFT) +#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) #define GPIO_AFRH12_SHIFT (16) -#define GPIO_AFRH12_MASK (15 << GPIO_AFRH4_SHIFT) +#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) #define GPIO_AFRH13_SHIFT (20) -#define GPIO_AFRH13_MASK (15 << GPIO_AFRH5_SHIFT) +#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) #define GPIO_AFRH14_SHIFT (24) -#define GPIO_AFRH14_MASK (15 << GPIO_AFRH6_SHIFT) +#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) #define GPIO_AFRH15_SHIFT (28) -#define GPIO_AFRH15_MASK (15 << GPIO_AFRH7_SHIFT) +#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h index 3d118fd8c..ad2e6f000 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h @@ -164,8 +164,8 @@ #define STM32_GPIOH_BASE 0x40021C00 /* 0x40021C00-0x40021fff: GPIO Port H */ #define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIO Port I */ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: Reset and Clock control RCC */ #define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash memory interface */ -#define STM32_RCC_BASE 0x40038000 /* 0x40023800-0x40023bff: Reset and Clock control RCC */ #define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: Backup SRAM (BKPSRAM) */ #define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */ #define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */ diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c index 57227f08f..6453c619f 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -118,7 +118,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32_RCC_APB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); /* Enable GPIOA, GPIOB, .... GPIOI*/ @@ -194,7 +194,7 @@ static inline void rcc_enableahb1(void) regval |= (RCC_AHB1ENR_OTGHSEN|RCC_AHB1ENR_OTGHSULPIEN); #endif - putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** |