diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-05-01 00:28:53 +0000 |
---|---|---|
committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-05-01 00:28:53 +0000 |
commit | 28d607865c3224b7398f9715039bb8d31537ee1c (patch) | |
tree | d5bb69176fb8575824c987127fbe22d9277f9aab /nuttx/arch/arm | |
parent | d120e9e5ed22796147c5bf429dc75eb6359b313b (diff) | |
download | px4-nuttx-28d607865c3224b7398f9715039bb8d31537ee1c.tar.gz px4-nuttx-28d607865c3224b7398f9715039bb8d31537ee1c.tar.bz2 px4-nuttx-28d607865c3224b7398f9715039bb8d31537ee1c.zip |
Low level UART support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@196 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm')
-rw-r--r-- | nuttx/arch/arm/src/lpc214x/chip.h | 53 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc214x/lpc214x_head.S | 99 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S | 113 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/lpc214x/lpc214x_uart.h | 141 |
4 files changed, 371 insertions, 35 deletions
diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h index 09f0ba342..f1e863c7d 100644 --- a/nuttx/arch/arm/src/lpc214x/chip.h +++ b/nuttx/arch/arm/src/lpc214x/chip.h @@ -40,6 +40,10 @@ * Included Files ************************************************************************************/ +/************************************************************************************ + * Definitions + ************************************************************************************/ + /* Memory Map ***********************************************************************/ #define LPC214X_FLASH_BASE 0x00000000 @@ -52,19 +56,50 @@ /* Register block base addresses */ +#define LPC214X_UART0_BASE 0xe000c000 /* UART0 Base Address */ +#define LPC214X_UART1_BASE 0xe0010000 /* UART1 Base Address */ +#define LPC214X_PINSEL_BASE 0xc002c000 /* Pin funtion select registers */ #define LPC214X_MAM_BASE 0xe01fc000 /* Memory Accelerator Module (MAM) Base Address */ #define LPC214X_MEMMAP 0xe01fc040 /* Memory Mapping Control */ #define LPC214X_PLL_BASE 0xe01fc080 /* Phase Locked Loop (PLL) Base Address */ #define LPC214X_VPBDIV 0xe01fc100 /* VPBDIV Address */ -#define LPC214X_PINSEL2 0xe002c014 /* PINSEL2 Address */ #define LPC214X_EMC_BASE 0xffe00000 /* External Memory Controller (EMC) Base Address */ +/* UART0/1 Register Offsets */ +#define LPC214X_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */ +#define LPC214X_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */ +#define LPC214X_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB) */ +#define LPC214X_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */ +#define LPC214X_DLM_OFFSET 0x04 /* R/W: Divisor Latch Register (MSB, DLAB=1) */ +#define LPC214X_IIR_OFFSET 0x08 /* R: Interrupt ID Register (DLAB=) */ +#define LPC214X_FCR_OFFSET 0x08 /* W: FIFO Control Register */ +#define LPC214X_LCR_OFFSET 0x0c /* R/W: Line Control Register */ +#define LPC214X_MCR_OFFSET 0x10 /* R/W: Modem Control REgister (2146/6/8 UART1 Only) */ +#define LPC214X_LSR_OFFSET 0x14 /* R: Scratch Pad Register */ +#define LPC214X_MSR_OFFSET 0x18 /* R/W: MODEM Status Register (2146/6/8 UART1 Only) */ +#define LPC214X_SCR_OFFSET 0x1c /* R/W: Line Status Register */ +#define LPC214X_ACR_OFFSET 0x20 /* R/W: Autobaud Control Register */ +#define LPC214X_FDR_OFFSET 0x28 /* R/W: Fractional Divider Register */ +#define LPC214X_TER_OFFSET 0x30 /* R/W: Transmit Enable Register */ + +/* Pin function select register offsets */ + +#define LPC214X_PINSEL0_OFFSET 0x00 /* Pin function select register 0 */ +#define LPC214X_PINSEL1_OFFSET 0x04 /* Pin function select register 1 */ +#define LPC214X_PINSEL2_OFFSET 0x14 /* Pin function select register 2 */ + +/* Pin function select registers (these are normally referenced as offsets) */ + +#define LPC214X_PINSEL0 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET) +#define LPC214X_PINSEL1 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET) +#define LPC214X_PINSEL2 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET) + /* Memory Accelerator Module (MAM) Regiser Offsets */ #define LPC214X_MAMCR_OFFSET 0x00 /* MAM Control Offset*/ #define LPC214x_MAMTIM_OFFSET 0x04 /* MAM Timing Offset */ -/* Phase Locked Loop (PLL) register offsets */ +/* Phase Locked Loop (PLL) Register Offsets */ #define LPC214X_PLLCON_OFFSET 0x00 /* PLL Control Offset*/ #define LPC214X_PLLCFG_OFFSET 0x04 /* PLL Configuration Offset */ @@ -73,14 +108,14 @@ /* PLL Control Register Bit Settings */ -#define LPC214X_PLLCON_PLLE (1<<0) /* PLL Enable */ -#define LPC214X_PLLCON_PLLC (1<<1) /* PLL Connect */ +#define LPC214X_PLLCON_PLLE (1 <<0) /* PLL Enable */ +#define LPC214X_PLLCON_PLLC (1 <<1) /* PLL Connect */ /* PLL Configuration Register Bit Settings */ -#define LPC214X_PLLCFG_MSEL (0x1f<<0) /* PLL Multiplier */ -#define LPC214X_PLLCFG_PSEL (0x03<<5) /* PLL Divider */ -#define LPC214X_PLLSTAT_PLOCK (1<<10) /* PLL Lock Status */ +#define LPC214X_PLLCFG_MSEL (0x1f << 0) /* PLL Multiplier */ +#define LPC214X_PLLCFG_PSEL (0x03 << 5) /* PLL Divider */ +#define LPC214X_PLLSTAT_PLOCK (1 << 10) /* PLL Lock Status */ /* External Memory Controller (EMC) definitions */ @@ -90,10 +125,6 @@ #define LPC214X_BCFG3_OFFSET 0x0c /* BCFG3 Offset */ /************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ * Inline Functions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S index 3d7c54db0..24180b670 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S @@ -87,7 +87,10 @@ * 156MHz <= Fcco <= 320MHz */ -#define LPC214X_PLLCFG_VALUE 0x00000024 + +#ifndef CONFIG_PLLCFG_VALUE /* Can be selected from config file */ +# define CONFIG_PLLCFG_VALUE 0x00000024 +#endif /* Memory Accelerator Module (MAM) initialization values * @@ -108,8 +111,13 @@ * 7 = 7 */ -#define LPC214X_MAMCR_VALUE 0x00000002 -#define LPC214x_MAMTIM_VALUE 0x00000004 +#ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */ +# define CONFIG_MAMCR_VALUE 0x00000002 +#endif + +#ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */ +# define CONFIG_MAMTIM_VALUE 0x00000004 +#endif /* VPBDIV initialization values * @@ -123,14 +131,18 @@ * 2 = XCLK Pin = CPU Clock / 2 */ -#define LPC214X_VPBDIV_VALUE 0x00000001 +#ifndef CONFIG_VPBDIV_VALUE /* Can be selected from config file */ +# define CONFIG_VPBDIV_VALUE 0x00000001 +#endif /* External Memory Pins definitions * * CS0..3, OE, WE, BLS0..3, D0..31, A2..23, JTAG Pins */ -#define LPC214X_PINSEL2_VALUE 0x0e6149e4 +#ifndef CONFIG_PINSEL2_VALUE /* Can be selected from config file */ +# define CONFIG_PINSEL2_VALUE 0x0e6149e4 +#endif /* External Memory Controller (EMC) initialization values * @@ -144,10 +156,30 @@ * BIT 28:29 MW: Memory Width (0=8-bit 1=16-bit 2=32-bit 3=Reserved) */ -#define LPC214X_BCFG0_VALUE 0x0000fbef -#define LPC214X_BCFG1_VALUE 0x0000fbef -#define LPC214X_BCFG2_VALUE 0x0000fbef -#define LPC214X_BCFG3_VALUE 0x0000fbef +#ifndef CONFIG_BCFG0_VALUE /* Can be selected from config file */ +# define CONFIG_BCFG0_VALUE 0x0000fbef +#endif + +#ifndef CONFIG_BCFG1_VALUE /* Can be selected from config file */ +# define CONFIG_BCFG1_VALUE 0x0000fbef +#endif + +#ifndef CONFIG_BCFG2_VALUE /* Can be selected from config file */ +# define CONFIG_BCFG2_VALUE 0x0000fbef +#endif + +#ifndef CONFIG_BCFG3_VALUE /* Can be selected from config file */ +# define CONFIG_BCFG3_VALUE 0x0000fbef +#endif + +/* The following are used to configure the ADC/DAC */ +#ifndef CONFIG_AD0CR_VALUE +# define CONFIG_AD0CR_VALUE 0x00200402; /* Setup A/D: 10-bit AIN0 @ 3MHz */ +#endif + +#ifndef CONFIG_PINSEL1_VALUE +# define CONFIG_PINSEL1_VALUE 0x01000000; /* Enable DAC */ +#endif /******************************************************************** * Macros @@ -169,7 +201,7 @@ .macro configpinsel2, base, val #ifdef CONFIG_EXTMEM_MODE ldr \base, =LPC214X_PINSEL2 - ldr \val, =LPC214X_PINSEL2_VALUE + ldr \val, =CONFIG_PINSEL2_VALUE str \val, [\base] #endif .endm @@ -181,22 +213,22 @@ ldr \base, =LPC214X_EMC_BASE #ifdef CONFIG_BCFG0_SETUP - ldr \val, =LPC214X_BCFG0_VALUE + ldr \val, =CONFIG_BCFG0_VALUE str \val, [\base, #LPC214X_BCFG0_OFFSET] #endif #ifdef CONFIG_BCFG1_SETUP - ldr \val, =LPC214X_BCFG1_VALUE + ldr \val, =CONFIG_BCFG1_VALUE str \val, [\base, #LPC214X_BCFG1_OFFSET] #endif #ifdef CONFIG_BCFG2_SETUP - ldr \val, =LPC214X_BCFG2_VALUE + ldr \val, =CONFIG_BCFG2_VALUE str \val, [\base, #LPC214X_BCFG2_OFFSET] #endif #ifdef CONFIG_BCFG3_SETUP - ldr \val, =LPC214X_BCFG3_VALUE + ldr \val, =CONFIG_BCFG3_VALUE str \val, [\base, #LPC214X_BCFG3_OFFSET] #endif #endif @@ -207,7 +239,7 @@ .macro configvpbdiv, base, val #ifdef CONFIG_VPBDIV_SETUP ldr \base, =LPC214X_VPBDIV - ldr \val, =LPC214X_VPBDIV_VALUE + ldr \val, =CONFIG_VPBDIV_VALUE str \val, [\base] #endif .endm @@ -222,7 +254,7 @@ /* Configure and Enable PLL */ - mov \val3, #LPC214X_PLLCFG_VALUE + mov \val3, #CONFIG_PLLCFG_VALUE str \val3, [\base, #LPC214X_PLLCFG_OFFSET] mov \val3, #LPC214X_PLLCON_PLLE str \val3, [\base, #LPC214X_PLLCON_OFFSET] @@ -249,9 +281,9 @@ .macro configmam, base, val #ifdef CONFIG_MAM_SETUP ldr \base, =LPC214X_MAM_BASE - mov \val, #LPC214x_MAMTIM_VALUE + mov \val, #CONFIG_MAMTIM_VALUE str \val, [\base, #LPC214x_MAMTIM_OFFSET] - mov \val, #LPC214X_MAMCR_VALUE + mov \val, #CONFIG_MAMCR_VALUE str \val, [\base, #LPC214X_MAMCR_OFFSET] #endif .endm @@ -259,15 +291,27 @@ /* Setup MEMMAP for the selected mode of operation */ .macro configmemmap, base, val - ldr r0, =LPC214X_MEMMAP + ldr \base, =LPC214X_MEMMAP #if defined(CONFIG_EXTMEM_MODE) - mov r1, #3 + mov \val, #3 #elif defined(CONFIG_RAM_MODE) - mov r1, #2 + mov \val, #2 #else /* Setting the default should not be necessary */ - mov r1, #1 + mov \val, #1 +#endif + str \val, [\base] + .endm + + .macro configdac, base, tmp +#ifdef CONFIG_ADC_SETUP + ldr \base, =LPC214X_AD0CR + ldr \tmp, =CONFIG_AD0CR_VALUE + str \tmp, [\base] + + ldr \base,=LPC214X_PINSEL1 + ldr \tmp, =CONFIG_PINSEL1_VALUE + str \tmp, [\base] #endif - str r1, [r0] .endm /******************************************************************** @@ -368,7 +412,16 @@ __start: /* Setup MEMMAP for the selected mode of operation */ configmemmap r0, r1 + + /* Configure the DAC and ADC */ + configdac r0, r1 + + /* Configure the uart so that we can get debug output as soon + * as possible. Modifies r0, r1, r2, and r14. + */ + + bl up_lowsetup showprogress 'A' /* Setup system stack (and get the BSS range) */ diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S index 8096ed3e9..bd9a86d0b 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S @@ -40,11 +40,70 @@ #include <nuttx/config.h> #include "up_internal.h" #include "up_arch.h" +#include "lpc214x_uart.h" /************************************************************************** * Private Definitions **************************************************************************/ +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define LPC214X_UART_BASE LPC214X_UART0_BASE +# define LPC214X_UART_PINSEL LPC214X_UART0_PINSEL +# define LPC214X_UART_PINMASK LPC214X_UART0_PINMASK +# define LPC214X_UART_BAUD CONFIG_UART0_BAUD +# define LPC214X_UART_BITS CONFIG_UART0_BITS +# define LPC214X_UART_PARITY CONFIG_UART0_PARITY +# ifdef CONFIG_UART0_2STOP +# define LPC214X_UART_2STOP 1 +# endif +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define LPC214X_UART_BASE LPC214X_UART1_BASE +# define LPC214X_UART_PINSEL LPC214X_UART1_PINSEL +# define LPC214X_UART_PINMASK LPC214X_UART1_PINMASK +# define LPC214X_UART_BAUD CONFIG_UART1_BAUD +# define LPC214X_UART_BITS CONFIG_UART1_BITS +# define LPC214X_UART_PARITY CONFIG_UART1_PARITY +# ifdef CONFIG_UART1_2STOP +# define LPC214X_UART_2STOP 1 +# endif +#else +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +#endif + +#if LPC214X_UART_BITS == 5 +# define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_5 +#elif LPC214X_UART_BITS == 6 +# define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_6 +#elif LPC214X_UART_BITS == 7 +# define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_7 +#elif LPC214X_UART_BITS == 8 +# define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_8 +#else +# error "No CONFIG_UARTn_BITS Setting" +#endif + +#if LPC214X_UART_PARITY == 0 +# define LPC214X_LCR_PAR LPC214X_LCR_PAR_NONE +#elif LPC214X_UART_PARITY == 1 +# define LPC214X_LCR_PAR LPC214X_LCR_PAR_ODD +#elif LPC214X_UART_PARITY == 2 +# define LPC214X_LCR_PAR LPC214X_LCR_PAR_EVEN +#elif LPC214X_UART_PARITY == 3 +# define LPC214X_LCR_PAR LPC214X_LCR_PAR_MARK +#elif LPC214X_UART_PARITY == 4 +# define LPC214X_LCR_PAR LPC214X_LCR_PAR_SPACE +#else +# error "No CONFIG_UARTn_PARITY Setting" +#endif + +#ifdef LPC214X_UART_2STOP +# define LPC214X_LCR_STOP LPC214X_LCR_STOP_2 +#else +# define LPC214X_LCR_STOP LPC214X_LCR_STOP_1 +#endif + +#define LPC214X_LCR_VALUE (LPC214X_LCR_CHAR | LPC214X_LCR_PAR | LPC214X_LCR_STOP) + /************************************************************************** * Private Types **************************************************************************/ @@ -83,9 +142,61 @@ .type up_lowputc, function up_lowputc: /* On entry, r0 holds the character to be printed */ -#warning "Not implemented" + + ldr r1, =LPC214X_UART_BASE + strb r0, [r1, #LPC214X_THR_OFFSET] + + /* Wait for the byte to be transferred */ + +1: ldr r0, [r1, #LPC214X_LSR_OFFSET] + ands r0, #LPC214X_LSR_TEMT /* Transmitter empty */ + beq 1b /* And return */ mov pc, lr + .size up_lowputc, . - up_lowputc + +/* This performs basic initialization of the UART. This can be called very + * early in initialization because it does not depend on having a stack. It + * modifies r0-r2 and r14. + */ + + .text + .globl up_lowsetup + .type up_lowsetup, function +up_lowsetup: + /* Configure PINSEL0 */ + + ldr r0, =LPC214X_PINSEL0 + ldr r1, [r0] + ldr r2, =LPC214X_UART_PINMASK + and r1, r2 + ldr r2, =LPC214X_UART_PINSEL + orr r1, r2 + str r1, [r0] + + /* Configure parity, data bits, stop bits and set DLAB=1 */ + + ldr r0, =LPC214X_UART0_BASE + mov r1, #(LPC214X_LCR_VALUE | LPC214X_LCR_DLAB_ENABLE) + strb r1, [r0, #LPC214X_LCR_OFFSET] + + /* Set the BAUD divisor */ + + mov r1, #(UART_BAUD(LPC214X_UART_BAUD) >> 8) + strb r1, [r0, #LPC214X_DLM_OFFSET] + + mov r1, #(UART_BAUD(LPC214X_UART_BAUD) & 0xff) + strb r1, [r0, #LPC214X_DLL_OFFSET] + + /* Clear DLAB */ + + mov r1, #LPC214X_LCR_VALUE + strb r1, [r0, #LPC214X_LCR_OFFSET] + + /* And return */ + + mov pc, lr + .size up_lowsetup, . - up_lowsetup .end diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_uart.h b/nuttx/arch/arm/src/lpc214x/lpc214x_uart.h new file mode 100755 index 000000000..636982589 --- /dev/null +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_uart.h @@ -0,0 +1,141 @@ +/************************************************************************************
+ * lpc214x/uart.h
+ *
+ * Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __LPC214X_UART_H
+#define __LPC214X_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <arch/board/board.h> /* For clock settings */
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* PINSEL0 bit definitions for UART0/1 */
+
+#define LPC214X_UART0_PINSEL 0x00000005 /* PINSEL0 value for UART0 */
+#define LPC214X_UART0_PINMASK 0x0000000f /* PINSEL0 mask for UART0 */
+
+#define LPC214X_UART1_PINSEL 0x00050000 /* PINSEL0 value for UART1 */
+#define LPC214X_UART1_PINMASK 0x000f0000 /* PINSEL0 mask for UART1 */
+
+/* Derive baud divisor setting from clock settings (see board.h) */
+
+#define UART_BAUD(baud) ((LPC214X_FOSC * LPC214X_PLL_M) / (baud * 16))
+
+/* Interrupt Enable Register (IER) bit definitions */
+
+#define LPC214X_IER_ERBFI (1 << 0) /* Enable receive data available int */
+#define LPC214X_IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */
+#define LPC214X_IER_ELSI (1 << 2) /* Enable receive line status int */
+#define LPC214X_IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt */
+
+/* Interrupt ID Register(IIR) bit definitions */
+
+#define LPC214X_IIR_NO_INT (1 << 0) /* No interrupts pending */
+#define LPC214X_IIR_MS_INT (0 << 1) /* MODEM Status */
+#define LPC214X_IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */
+#define LPC214X_IIR_RDA_INT (2 << 1) /* Receive Data Available */
+#define LPC214X_IIR_RLS_INT (3 << 1) /* Receive Line Status */
+#define LPC214X_IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */
+#define LPC214X_IIR_MASK 0x0e
+
+/* FIFO Control Register (FCR) bit definitions */
+
+#define LPC214X_FCR_FIFO_ENABLE (1 << 0) /* FIFO wnable */
+#define LPC214X_FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */
+#define LPC214X_FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */
+#define LPC214X_FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */
+#define LPC214X_FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */
+#define LPC214X_FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */
+#define LPC214X_FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */
+
+/* Line Control Register (LCR) bit definitions */
+
+#define LPC214X_LCR_CHAR_5 (0 << 0) /* 5-bit character length */
+#define LPC214X_LCR_CHAR_6 (1 << 0) /* 6-bit character length */
+#define LPC214X_LCR_CHAR_7 (2 << 0) /* 7-bit character length */
+#define LPC214X_LCR_CHAR_8 (3 << 0) /* 8-bit character length */
+#define LPC214X_LCR_STOP_1 (0 << 2) /* 1 stop bit */
+#define LPC214X_LCR_STOP_2 (1 << 2) /* 2 stop bits */
+#define LPC214X_LCR_PAR_NONE (0 << 3) /* No parity */
+#define LPC214X_LCR_PAR_ODD (1 << 3) /* Odd parity */
+#define LPC214X_LCR_PAR_EVEN (3 << 3) /* Even parity */
+#define LPC214X_LCR_PAR_MARK (5 << 3) /* Mark "1" parity */
+#define LPC214X_LCR_PAR_SPACE (7 << 3) /* Space "0" parity */
+#define LPC214X_LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */
+#define LPC214X_LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */
+
+/* Modem Control Register (MCR) bit definitions */
+
+#define LPC214X_MCR_DTR (1 << 0) /* Data terminal ready */
+#define LPC214X_MCR_RTS (1 << 1) /* Request to send */
+#define LPC214X_MCR_LB (1 << 4) /* Loopback */
+
+/* Line Status Register (LSR) bit definitions */
+
+#define LPC214X_LSR_RDR (1 << 0) /* Receive data ready */
+#define LPC214X_LSR_OE (1 << 1) /* Overrun error */
+#define LPC214X_LSR_PE (1 << 2) /* Parity error */
+#define LPC214X_LSR_FE (1 << 3) /* Framing error */
+#define LPC214X_LSR_BI (1 << 4) /* Break interrupt */
+#define LPC214X_LSR_THRE (1 << 5) /* THR empty */
+#define LPC214X_LSR_TEMT (1 << 6) /* Transmitter empty */
+#define LPC214X_LSR_RXFE (1 << 7) /* Error in receive FIFO */
+#define LPC214X_LSR_ERR_MASK 0x1e
+
+/* Modem Status Register (MSR) bit definitions */
+
+#define LPC214X_MSR_DCTS (1 << 0) /* Delta clear to send */
+#define LPC214X_MSR_DDSR (1 << 1) /* Delta data set ready */
+#define LPC214X_MSR_TERI (1 << 2) /* Trailing edge ring indicator */
+#define LPC214X_MSR_DDCD (1 << 3) /* Delta data carrier detect */
+#define LPC214X_MSR_CTS (1 << 4) /* Clear to send */
+#define LPC214X_MSR_DSR (1 << 5) /* Data set ready */
+#define LPC214X_MSR_RI (1 << 6) /* Ring indicator */
+#define LPC214X_MSR_DCD (1 << 7) /* Data carrier detect */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Function Prototypes
+ ************************************************************************************/
+
+#endif /* __LPC214X_UART_H */
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