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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-05-24 11:11:48 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-05-24 11:11:48 -0600 |
| commit | 4ec39dfdc2134d73a809f1159460156a101c89a5 (patch) | |
| tree | a5633412cd7bab19d77ff44a953d4ba282bc34d4 /nuttx/arch/arm | |
| parent | d890cd67c3ef9e702a71bb5ed2f8a5e9e6d4cfac (diff) | |
| download | px4-nuttx-4ec39dfdc2134d73a809f1159460156a101c89a5.tar.gz px4-nuttx-4ec39dfdc2134d73a809f1159460156a101c89a5.tar.bz2 px4-nuttx-4ec39dfdc2134d73a809f1159460156a101c89a5.zip | |
Fix bugs in SLCD test and in SLCD CODEC
Diffstat (limited to 'nuttx/arch/arm')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_lse.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_lse.c b/nuttx/arch/arm/src/stm32/stm32_lse.c index 1080b4b20..56d68b1dc 100644 --- a/nuttx/arch/arm/src/stm32/stm32_lse.c +++ b/nuttx/arch/arm/src/stm32/stm32_lse.c @@ -41,6 +41,7 @@ #include "up_arch.h" +#include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_waste.h" @@ -78,6 +79,16 @@ #ifdef CONFIG_STM32_STM32L15XX void stm32_rcc_enablelse(void) { + uint16_t pwrcr; + + /* The LSE is in the RTC domain and write access is denied to this domain + * after reset, you have to enable write access using DBP bit in the PWR CR + * register before to configuring the LSE. + */ + + pwrcr = getreg16(STM32_PWR_CR); + putreg16(pwrcr | PWR_CR_DBP, STM32_PWR_CR); + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit * the RCC CSR register. */ @@ -110,6 +121,10 @@ void stm32_rcc_enablelse(void) modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_RTCEN); #endif #endif + + /* Restore the previous state of the DBP bit */ + + putreg16(pwrcr, STM32_PWR_CR); } #else |