Make sure that there is one space between while and condition

8 files changed, 11 insertions, 11 deletions

diff --git a/nuttx/arch/arm/src/common/up_lowputs.c b/nuttx/arch/arm/src/common/up_lowputs.c
index 890167e0e..b3234637f 100644
--- a/nuttx/arch/arm/src/common/up_lowputs.c
+++ b/nuttx/arch/arm/src/common/up_lowputs.c
@@ -67,7 +67,7 @@
 
 void up_lowputs(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_lowputc(*str++);
     }
diff --git a/nuttx/arch/arm/src/sama5/sam_nand.c b/nuttx/arch/arm/src/sama5/sam_nand.c
index 3f1a041ef..9e4bf0e8b 100644
--- a/nuttx/arch/arm/src/sama5/sam_nand.c
+++ b/nuttx/arch/arm/src/sama5/sam_nand.c
@@ -1738,7 +1738,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
 
   /* Wait until the kernel of the PMECC is not busy */
 
-  while((nand_getreg(SAM_HSMC_PMECCSR) & HSMC_PMECCSR_BUSY) != 0);
+  while ((nand_getreg(SAM_HSMC_PMECCSR) & HSMC_PMECCSR_BUSY) != 0);
   return OK;
 }
 #endif
diff --git a/nuttx/arch/arm/src/stm32/stm32_flash.c b/nuttx/arch/arm/src/stm32/stm32_flash.c
index 20b0cfe10..f725fb7f7 100644
--- a/nuttx/arch/arm/src/stm32/stm32_flash.c
+++ b/nuttx/arch/arm/src/stm32/stm32_flash.c
@@ -148,7 +148,7 @@ int up_progmem_erasepage(uint16_t page)
   putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR);
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT);
 
-  while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
+  while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
 
   modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0);
 
@@ -232,7 +232,7 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count)
 
       putreg16(*hword, addr);
 
-      while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
+      while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
 
       /* Verify */
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.c b/nuttx/arch/arm/src/stm32/stm32_pwr.c
index 1c9513541..21a397599 100644
--- a/nuttx/arch/arm/src/stm32/stm32_pwr.c
+++ b/nuttx/arch/arm/src/stm32/stm32_pwr.c
@@ -129,14 +129,14 @@ void stm32_pwr_setvos(uint16_t vos)
    * 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
    */
 
-  while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
+  while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
 
   regval  = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
   regval &= ~PWR_CR_VOS_MASK;
   regval |= (vos & PWR_CR_VOS_MASK);
   stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
 
-  while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
+  while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
 }
 #endif
 
diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
index f887f8995..f46f0d104 100644
--- a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -548,7 +548,7 @@ static void stm32_stdclockconfig(void)
 
   /* Wait for PLL2 ready */
 
-  while((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
 
   /* Setup PLL3 for MII/RMII clock on MCO */
 
diff --git a/nuttx/arch/arm/src/stm32/stm32f30xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f30xxx_rcc.c
index c18f1de3e..1209013d8 100644
--- a/nuttx/arch/arm/src/stm32/stm32f30xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f30xxx_rcc.c
@@ -457,7 +457,7 @@ static void stm32_stdclockconfig(void)
 
   /* Wait for PLL2 ready */
 
-  while((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
 
   /* Setup PLL3 for MII/RMII clock on MCO */
 
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
index bba3c2142..4c74fa912 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -686,14 +686,14 @@ static void stm32_stdclockconfig(void)
       regval  = getreg32(STM32_PWR_CR);
       regval |= PWR_CR_ODEN;
       putreg32(regval, STM32_PWR_CR);
-      while((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
+      while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
         {
         }
 
       regval = getreg32(STM32_PWR_CR);
       regval |= PWR_CR_ODSWEN;
       putreg32(regval, STM32_PWR_CR);
-      while((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
+      while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
         {
         }
 
diff --git a/nuttx/arch/arm/src/tiva/tiva_flash.c b/nuttx/arch/arm/src/tiva/tiva_flash.c
index 154617fd6..fe463222c 100644
--- a/nuttx/arch/arm/src/tiva/tiva_flash.c
+++ b/nuttx/arch/arm/src/tiva/tiva_flash.c
@@ -217,7 +217,7 @@ static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
 
       /* wait until write has finished */
 
-      while(getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
+      while (getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
     }
 
   return nblocks;