Add matrix header file

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2483 42af7a65-404d-4744-a932-0658087f49c3

2 files changed, 203 insertions, 1 deletions

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_matrix.h b/nuttx/arch/arm/src/sam3u/sam3u_matrix.h
new file mode 100755
index 000000000..0b6d044e2
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam3u_matrix.h
@@ -0,0 +1,198 @@
+/****************************************************************************************

+ * arch/arm/src/sam3u/sam3u_matric.h

+ *

+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions

+ * are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright

+ *    notice, this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright

+ *    notice, this list of conditions and the following disclaimer in

+ *    the documentation and/or other materials provided with the

+ *    distribution.

+ * 3. Neither the name NuttX nor the names of its contributors may be

+ *    used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ ****************************************************************************************/

+

+#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H

+#define __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H

+

+/****************************************************************************************

+ * Included Files

+ ****************************************************************************************/

+

+#include <nuttx/config.h>

+

+#include "chip.h"

+#include "sam3u_memorymap.h"

+

+/****************************************************************************************

+ * Pre-processor Definitions

+ ****************************************************************************************/

+

+/* MATRIX register offsets **************************************************************/

+

+#define SAM3U_MATRIX_MCFG_OFFSET(n)     ((n)<<2)

+#define SAM3U_MATRIX_MCFG0_OFFSET       0x0000 /* Master Configuration Register 0 */

+#define SAM3U_MATRIX_MCFG1_OFFSET       0x0004 /* Master Configuration Register 1 */

+#define SAM3U_MATRIX_MCFG2_OFFSET       0x0008 /* Master Configuration Register 2 */

+#define SAM3U_MATRIX_MCFG3_OFFSET       0x000c /* Master Configuration Register 3 */

+#define SAM3U_MATRIX_MCFG4_OFFSET       0x0010 /* Master Configuration Register 4 */

+                                               /* 0x0014-0x003c: Reserved */

+#define SAM3U_MATRIX_SCFG_OFFSET(n)     (0x0040+((n)<<2))

+#define SAM3U_MATRIX_SCFG0_OFFSET       0x0040 /* Slave Configuration Register 0 */

+#define SAM3U_MATRIX_SCFG1_OFFSET       0x0044 /* Slave Configuration Register 1 */

+#define SAM3U_MATRIX_SCFG2_OFFSET       0x0048 /* Slave Configuration Register 2 */

+#define SAM3U_MATRIX_SCFG3_OFFSET       0x004c /* Slave Configuration Register 3 */

+#define SAM3U_MATRIX_SCFG4_OFFSET       0x0050 /* Slave Configuration Register 4 */

+#define SAM3U_MATRIX_SCFG5_OFFSET       0x0054 /* Slave Configuration Register 5 */

+#define SAM3U_MATRIX_SCFG6_OFFSET       0x0058 /* Slave Configuration Register 6 */

+#define SAM3U_MATRIX_SCFG7_OFFSET       0x005c /* Slave Configuration Register 7 */

+#define SAM3U_MATRIX_SCFG8_OFFSET       0x0060 /* Slave Configuration Register 8 */

+#define SAM3U_MATRIX_SCFG9_OFFSET       0x0064 /* Slave Configuration Register 9 */

+                                               /* 0x0068-0x007c: Reserved */

+#define SAM3U_MATRIX_SCFG_OFFSET(n)     (0x0080+((n)<<3))

+#define SAM3U_MATRIX_PRAS0_OFFSET       0x0080 /* Priority Register A for Slave 0 */

+                                               /* 0x0084: Reserved */

+#define SAM3U_MATRIX_PRAS1_OFFSET       0x0088 /* Priority Register A for Slave 1 */

+                                               /* 0x008c: Reserved */

+#define SAM3U_MATRIX_PRAS2_OFFSET       0x0090 /* Priority Register A for Slave 2 */

+                                               /* 0x0094: Reserved */

+#define SAM3U_MATRIX_PRAS3_OFFSET       0x0098 /* Priority Register A for Slave 3 */

+                                               /* 0x009c: Reserved */

+#define SAM3U_MATRIX_PRAS4_OFFSET       0x00a0 /* Priority Register A for Slave 4 */

+                                               /* 0x00a4: Reserved */

+#define SAM3U_MATRIX_PRAS5_OFFSET       0x00a8 /* Priority Register A for Slave 5 */

+                                               /* 0x00ac: Reserved */

+#define SAM3U_MATRIX_PRAS6_OFFSET       0x00b0 /* Priority Register A for Slave 6 */

+                                               /* 0x00b4: Reserved */

+#define SAM3U_MATRIX_PRAS7_OFFSET       0x00b8 /* Priority Register A for Slave 7 */

+                                               /* 0x00bc: Reserved */

+#define SAM3U_MATRIX_PRAS8_OFFSET       0x00c0 /* Priority Register A for Slave 8 */

+                                               /* 0x00c4: Reserved */

+#define SAM3U_MATRIX_PRAS9_OFFSET       0x00c8 /* Priority Register A for Slave 9 */

+                                               /* 0x00cc-0x00fc: Reserved */

+#define SAM3U_MATRIX_MRCR_OFFSET        0x0100 /* Master Remap Control Register */

+                                               /* 0x0104-0x010c: Reserved */

+#define SAM3U_MATRIX_WPMR_OFFSET        0x01e4 /* Write Protect Mode Register */

+#define SAM3U_MATRIX_WPSR_OFFSET        0x01e8 /* Write Protect Status Register */

+                                               /* 0x0110 - 0x01fc: Reserved */

+

+/* MATRIX register adresses *************************************************************/

+

+#define SAM3U_MATRIX_MCFG(n))           (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n))

+#define SAM3U_MATRIX_MCFG0              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET)

+#define SAM3U_MATRIX_MCFG1              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET)

+#define SAM3U_MATRIX_MCFG2              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET)

+#define SAM3U_MATRIX_MCFG3              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET)

+#define SAM3U_MATRIX_MCFG4              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET)

+ 

+#define SAM3U_MATRIX_SCFG(n)            (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n))

+#define SAM3U_MATRIX_SCFG0              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET)

+#define SAM3U_MATRIX_SCFG1              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET)

+#define SAM3U_MATRIX_SCFG2              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET)

+#define SAM3U_MATRIX_SCFG3              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET)

+#define SAM3U_MATRIX_SCFG4              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET)

+#define SAM3U_MATRIX_SCFG5              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET)

+#define SAM3U_MATRIX_SCFG6              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET)

+#define SAM3U_MATRIX_SCFG7              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET)

+#define SAM3U_MATRIX_SCFG8              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET)

+#define SAM3U_MATRIX_SCFG9              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET)

+

+#define SAM3U_MATRIX_SCFG(n)            (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n))

+#define SAM3U_MATRIX_PRAS0              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET)

+#define SAM3U_MATRIX_PRAS1              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET)

+#define SAM3U_MATRIX_PRAS2              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET)

+#define SAM3U_MATRIX_PRAS3              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET)

+#define SAM3U_MATRIX_PRAS4              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET)

+#define SAM3U_MATRIX_PRAS5              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET)

+#define SAM3U_MATRIX_PRAS6              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET)

+#define SAM3U_MATRIX_PRAS7              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET)

+#define SAM3U_MATRIX_PRAS8              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET)

+#define SAM3U_MATRIX_PRAS9              (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET)

+

+#define SAM3U_MATRIX_MRCR               (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET)

+#define SAM3U_MATRIX_WPMR               (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET)

+#define SAM3U_MATRIX_WPSR               (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET)

+

+/* MATRIX register bit definitions ******************************************************/

+

+#define MATRIX_MCFG_ULBT_SHIFT          (0)       /* Bits 0-2:  Undefined Length Burst Type */

+#define MATRIX_MCFG_ULBT_MASK           (7 << MATRIX_MCFG_ULBT_SHIFT)

+#  define MATRIX_MCFG_ULBT_INF          (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst

+#  define MATRIX_MCFG_ULBT_SINGLE       (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access

+#  define MATRIX_MCFG_ULBT_4BEAT        (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst

+#  define MATRIX_MCFG_ULBT_8BEAT        (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst

+#  define MATRIX_MCFG_ULBT_16BEAT       (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst

+

+#define MATRIX_SCFG_SLOT_CYCLE_SHIFT    (0)       /* Bits 0-7:  Maximum Number of Allowed Cycles for a Burst */

+#define MATRIX_SCFG_SLOT_CYCLE_MASK     (0xff << MATRIX_SCFG_SLOT_CYCLE_SHIFT)

+#define MATRIX_SCFG_DEFMSTR_TYPE_SHIFT  (16)      /* Bits 16-17:  Default Master Type */

+#define MATRIX_SCFG_DEFMSTR_TYPE_MASK   (3 << MATRIX_SCFG_DEFMSTR_TYPE_SHIFT)

+#define MATRIX_SCFG_FIXED_DEFMSTR_SHIFT (18)      /* Bits 18-20:   Fixed Default Master */

+#define MATRIX_SCFG_FIXED_DEFMSTR_MASK  (7 << MATRIX_SCFG_FIXED_DEFMSTR_SHIFT)

+#define MATRIX_SCFG_ARBT_SHIFT          (24)      /* Bits 24-25:   Arbitration Type */

+#define MATRIX_SCFG_ARBT_MASK           (3 << MATRIX_SCFG_ARBT_SHIFT)

+#  define MATRIX_SCFG_ARBT_RR           (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration

+#  define MATRIX_SCFG_ARBT_FIXED        (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration

+

+#define MATRIX_PRAS_MPR_SHIFT(x)        ((n)<<2)

+#define MATRIX_PRAS_MPR_MASK(x)         (3 << MATRIX_PRAS_MPR_SHIFT(x))

+#define MATRIX_PRAS_M0PR_SHIFT          (0)       /* Bits 0-1:  Master 0 Priority */

+#define MATRIX_PRAS_M0PR_MASK           (3 << MATRIX_PRAS_M0PR_SHIFT)

+#define MATRIX_PRAS_M1PR_SHIFT          (4)       /* Bits 4-5:   Master 1 Priority */

+#define MATRIX_PRAS_M1PR_MASK           (3 << MATRIX_PRAS_M1PR_SHIFT)

+#define MATRIX_PRAS_M2PR_SHIFT          (8)       /* Bits 8-9:  Master 2 Priority */

+#define MATRIX_PRAS_M2PR_MASK           (3 << MATRIX_PRAS_M2PR_SHIFT)

+#define MATRIX_PRAS_M3PR_SHIFT          (12)      /* Bits 12-13:  Master 3 Priority */

+#define MATRIX_PRAS_M3PR_MASK           (3 << MATRIX_PRAS_M3PR_SHIFT)

+#define MATRIX_PRAS_M4PR_SHIFT          (16)      /* Bits 16-bb17  Master 4 Priority */

+#define MATRIX_PRAS_M4PR_MASK           (3 << MATRIX_PRAS_M4PR_SHIFT)

+

+#define MATRIX_MRCR_RCB(x)              (1 << (x))

+#define MATRIX_MRCR_RCB0                (1 << 0)  /* Bit 0:  Remap Command Bit for AHB Master 0 */

+#define MATRIX_MRCR_RCB1                (1 << 1)  /* Bit 1:  Remap Command Bit for AHB Master 1 */

+#define MATRIX_MRCR_RCB2                (1 << 2)  /* Bit 2:  Remap Command Bit for AHB Master 2 */

+#define MATRIX_MRCR_RCB3                (1 << 3)  /* Bit 3:  Remap Command Bit for AHB Master 3 */

+#define MATRIX_MRCR_RCB4                (1 << 4)  /* Bit 4:  Remap Command Bit for AHB Master 4 */

+

+#define MATRIX_WPMR_WPEN                (1 << 0)  /* Bit 0:  Write Protect Enable */

+#define MATRIX_WPMR_WPKEY_SHIFT         (8)       /* Bits 8-31:   Write Protect KEY (Write-only) */

+#define MATRIX_WPMR_WPKEY_MASK          (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT)

+

+#define MATRIX_WPSR_WPVS                (1 << 0)  /* Bit 0:  Enable Write Protect */

+#define MATRIX_WPSR_WPVSRC_SHIFT        (8)       /* Bits 8-23:  Write Protect Violation Source */

+#define MATRIX_WPSR_WPVSRC_MASK         (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)

+

+/****************************************************************************************

+ * Public Types

+ ****************************************************************************************/

+

+/****************************************************************************************

+ * Public Data

+ ****************************************************************************************/

+

+/****************************************************************************************

+ * Public Functions

+ ****************************************************************************************/

+

+#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H */

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
index 09c032cc5..268cfde3b 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
+++ b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
@@ -66,12 +66,14 @@
 #  define SAM3U_SSC_BASE        0x40000400 /* 0x40000400-0x400007ff:   Synchronous Serial Controller */

 #  define SAM3U_SPI_BASE        0x40000800 /* 0x40000800-0x40000bff:   Serial Peripheral Interface */

                                            /* 0x40000c00-0x4007ffff:   Reserved */

+#  define SAM3U_TC_BASE(n)      (0x40080000+((n)<<6))

 #  define SAM3U_TC0_BASE        0x40080000 /* 0x40080000-0x4008003f:   Timer Counter 0 */

 #  define SAM3U_TC1_BASE        0x40080040 /* 0x40080040-0x4008007f:   Timer Counter 1 */

 #  define SAM3U_TC2_BASE        0x40080080 /* 0x40080080-0x400800bf:   Timer Counter 2 */

 #  define SAM3U_TWI0_BASE       0x40084000 /* 0x40084000-0x40087fff:   Two-Wire Interface 0 */

 #  define SAM3U_TWI1_BASE       0x40088000 /* 0x40088000-0x4008bfff:   Two-Wire Interface 1 */

 #  define SAM3U_PWM_BASE        0x4008c000 /* 0x4008c000-0x4008ffff:   Pulse Width Modulation Controller */

+#  define SAM3U_USART_BASE(n)   (0x40090000+((n)<<14))

 #  define SAM3U_USART0_BASE     0x40090000 /* 0x40090000-0x40093fff:   USART0 */

 #  define SAM3U_USART1_BASE     0x40094000 /* 0x40094000-0x40097fff:   USART1 */

 #  define SAM3U_USART2_BASE     0x40098000 /* 0x40098000-0x4009bfff:   USART2 */

@@ -88,6 +90,7 @@
 #  define SAM3U_BBPERIPH__BASE  0x42000000 /* 0x42000000-0x43ffffff:   32Mb bit-band alias */

                                            /* 0x44000000-0x5fffffff:   Reserved */

 #define   SAM3U_EXTSRAM_BASE    0x60000000 /* 0x60000000-0x9fffffff: External SRAM */

+#  define SAM3U_EXTCS_BASE(n)   (0x60000000*((n)<<24))

 #  define SAM3U_EXTCS0_BASE     0x60000000 /* 0x60000000-0x60ffffff:   Chip select 0 */

 #  define SAM3U_EXTCS1_BASE     0x61000000 /* 0x61000000-0x601fffff:   Chip select 1 */

 #  define SAM3U_EXTCS2_BASE     0x62000000 /* 0x62000000-0x62ffffff:   Chip select 2 */

@@ -105,9 +108,10 @@
 #define SAM3U_PMC_BASE          0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */

 #define SAM3U_UART_BASE         0x400e0600 /* 0x400e0600-0x400e073f: UART */

 #define SAM3U_CHIPID_BASE       0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */

-#define SAM3U_EEFC_BASE(n)      (0x400e0800+((n)*0x200)

+#define SAM3U_EEFC_BASE(n)      (0x400e0800+((n)<<9))

 #define SAM3U_EEFC0_BASE        0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */

 #define SAM3U_EEFC1_BASE        0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */

+#define SAM3U_PIO_BASE(n)       (0x400e0c00+((n)<<9))

 #define SAM3U_PIOA_BASE         0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */

 #define SAM3U_PIOB_BASE         0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */

 #define SAM3U_PIOC_BASE         0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */