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author | Gregory Nutt <gnutt@nuttx.org> | 2013-04-24 18:29:26 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-04-24 18:29:26 -0600 |
commit | 7a45a69800188774ffa2988aab98832462fe7cdf (patch) | |
tree | dd4f4769bf13aec2f68539933ce8facd06b0bae4 /nuttx/arch/arm | |
parent | 2b0558a4003a031a7e6dc0c95670473e018d8b98 (diff) | |
download | px4-nuttx-7a45a69800188774ffa2988aab98832462fe7cdf.tar.gz px4-nuttx-7a45a69800188774ffa2988aab98832462fe7cdf.tar.bz2 px4-nuttx-7a45a69800188774ffa2988aab98832462fe7cdf.zip |
Fix KL25Z clock definitions in board.h
Diffstat (limited to 'nuttx/arch/arm')
-rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_mcg.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_sim.h | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/kl_clockconfig.c | 24 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/kl_lowputc.c | 29 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/kl_serial.c | 17 |
5 files changed, 36 insertions, 40 deletions
diff --git a/nuttx/arch/arm/src/kl/chip/kl_mcg.h b/nuttx/arch/arm/src/kl/chip/kl_mcg.h index 6b1d2e91d..4e6f2d9df 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_mcg.h +++ b/nuttx/arch/arm/src/kl/chip/kl_mcg.h @@ -134,7 +134,7 @@ #define MCG_C5_PRDIV_SHIFT (0) /* Bits 0-4: PLL External Reference Divider */ #define MCG_C5_PRDIV_MASK (31 << MCG_C5_PRDIV_SHIFT) -# define MCG_C5_PRDIV(n) (n << MCG_C5_PRDIV_SHIFT) /* Divide factor n=1..25 */ +# define MCG_C5_PRDIV(n) (((n)-1) << MCG_C5_PRDIV_SHIFT) /* Divide factor n=1..25 */ #define MCG_C5_PLLSTEN (1 << 5) /* Bit 5: PLL Stop Enable */ #define MCG_C5_PLLCLKEN (1 << 6) /* Bit 6: PLL Clock Enable */ /* Bit 7: Reserved */ diff --git a/nuttx/arch/arm/src/kl/chip/kl_sim.h b/nuttx/arch/arm/src/kl/chip/kl_sim.h index 65f1428f9..0d2650978 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_sim.h +++ b/nuttx/arch/arm/src/kl/chip/kl_sim.h @@ -383,7 +383,7 @@ /* Bits 0-15: Reserved */ #define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */ #define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) -# define SIM_CLKDIV1_OUTDIV4(n) ((n) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by n, n=1..16 */ +# define SIM_CLKDIV1_OUTDIV4(n) (((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by n, n=1..16 */ # define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */ # define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */ # define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */ @@ -440,7 +440,7 @@ # define SIM_CLKDIV1_OUTDIV2_16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */ #define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */ #define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) -# define SIM_CLKDIV1_OUTDIV1(n) ((n) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by n, n=1..16 */ +# define SIM_CLKDIV1_OUTDIV1(n) (((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by n, n=1..16 */ # define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */ # define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */ # define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */ diff --git a/nuttx/arch/arm/src/kl/kl_clockconfig.c b/nuttx/arch/arm/src/kl/kl_clockconfig.c index 25ee2ba35..d996383d7 100644 --- a/nuttx/arch/arm/src/kl/kl_clockconfig.c +++ b/nuttx/arch/arm/src/kl/kl_clockconfig.c @@ -106,9 +106,11 @@ void kl_pllconfig(void) regval32 |= SIM_SCGC5_PORTA; putreg32(regval32, KL_SIM_SCGC5); - /* Divide-by-2 for clock 1 and clock 4 (OUTDIV1=1, OUTDIV4=1) */ + /* Divide-by-2 for clock 1 and clock 4. OUTDIV1 and OUTDIV4 determined by + * settings in the board.h header file. + */ - regval32 = (SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1)); + regval32 = (SIM_CLKDIV1_OUTDIV1(BOARD_OUTDIV1) | SIM_CLKDIV1_OUTDIV4(BOARD_OUTDIV4)); putreg32(regval32, KL_SIM_CLKDIV1); /* System oscillator drives 32 kHz clock for various peripherals (OSC32KSEL=0) */ @@ -133,11 +135,11 @@ void kl_pllconfig(void) regval32 = getreg32(KL_PORTA_PCR18); regval32 &= ~(PORT_PCR_ISF | PORT_PCR_MUX_ALT7); - putreg32(regval32, KL_PORTA_PCR18); + putreg32(regval32, KL_PORTA_PCR18); regval32 = getreg32(KL_PORTA_PCR19); regval32 &= ~(PORT_PCR_ISF | PORT_PCR_MUX_ALT7); - putreg32(regval32, KL_PORTA_PCR19); + putreg32(regval32, KL_PORTA_PCR19); /* Switch to FBE Mode */ /* OSC0_CR: ERCLKEN=0, ??=0, EREFSTEN=0, ??=0, SC2P=0, SC4P=0, SC8P=0, SC16P=0 */ @@ -160,15 +162,19 @@ void kl_pllconfig(void) regval8 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK); putreg8(regval8, KL_MCG_C4); - /* MCG_C5: ??=0, PLLCLKEN0=0, PLLSTEN0=0, PRDIV0=1 */ + /* MCG_C5: ??=0, PLLCLKEN0=0, PLLSTEN0=0, PRDIV0 determined by board + * settings in the board.h header file. + */ - regval8 = MCG_C5_PRDIV(1); + regval8 = MCG_C5_PRDIV(BOARD_PRDIV0); putreg8(regval8, KL_MCG_C5); - /* MCG_C6: LOLIE0=0, PLLS=0, CME0=0, VDIV0=0 */ + /* MCG_C6: LOLIE0=0, PLLS=0, CME0=0, VDIV0 determined by board + * settings in the board.h header file. + */ + + putreg8(MCG_C6_VDIV(BOARD_VDIV0), KL_MCG_C6); - putreg8(0, KL_MCG_C6); - /* Check that the source of the FLL reference clock is the external * reference clock. */ diff --git a/nuttx/arch/arm/src/kl/kl_lowputc.c b/nuttx/arch/arm/src/kl/kl_lowputc.c index 208bf2c0f..9f589ad1c 100644 --- a/nuttx/arch/arm/src/kl/kl_lowputc.c +++ b/nuttx/arch/arm/src/kl/kl_lowputc.c @@ -59,28 +59,23 @@ /************************************************************************** * Private Definitions **************************************************************************/ - -#warning "Revisit" -#undef BOARD_CORECLK_FREQ -#define BOARD_CORECLK_FREQ 48000000 - /* Select UART parameters for the selected console */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_BASE KL_UART0_BASE -# define CONSOLE_FREQ 48000000 +# define CONSOLE_FREQ BOARD_CORECLK_FREQ # define CONSOLE_BAUD CONFIG_UART0_BAUD # define CONSOLE_BITS CONFIG_UART0_BITS # define CONSOLE_PARITY CONFIG_UART0_PARITY #elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_BASE KL_UART1_BASE -# define CONSOLE_FREQ 48000000 +# define CONSOLE_FREQ BOARD_BUSCLK_FREQ # define CONSOLE_BAUD CONFIG_UART1_BAUD # define CONSOLE_BITS CONFIG_UART1_BITS # define CONSOLE_PARITY CONFIG_UART1_PARITY #elif defined(CONFIG_UART2_SERIAL_CONSOLE) # define CONSOLE_BASE KL_UART2_BASE -# define CONSOLE_FREQ 48000000 +# define CONSOLE_FREQ BOARD_BUSCLK_FREQ # define CONSOLE_BAUD CONFIG_UART2_BAUD # define CONSOLE_BITS CONFIG_UART2_BITS # define CONSOLE_PARITY CONFIG_UART2_PARITY @@ -113,7 +108,7 @@ static uint8_t g_sizemap[8] = {1, 4, 8, 16, 32, 64, 128, 0}; /************************************************************************** * Private Functions **************************************************************************/ - + /************************************************************************** * Public Functions **************************************************************************/ @@ -314,7 +309,7 @@ void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, { regval |= UART_C1_M; } - + /* The only other option is 8-bit operation */ else @@ -328,7 +323,7 @@ void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, sbr = clock / (baud << 4); DEBUGASSERT(sbr < 0x2000); - + /* Save the new baud divisor, retaining other bits in the UARTx_BDH * register. */ @@ -340,7 +335,7 @@ void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, regval = sbr & 0xff; putreg8(regval, uart_base+KL_UART_BDL_OFFSET); - + /* Calculate a fractional divider to get closer to the requested baud. * The fractional divider, BRFA, is a 5 bit fractional value that is * logically added to the SBR: @@ -353,7 +348,7 @@ void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, tmp = clock - (sbr * (baud << 4)); brfa = (tmp << 5) / (baud << 4); - + /* Set the BRFA field (retaining other bits in the UARTx_C4 register) */ regval = getreg8(uart_base+KL_UART_C4_OFFSET) & UART_C4_BRFA_MASK; @@ -379,14 +374,14 @@ void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, depth = (3 * depth) >> 2; } putreg8(depth , uart_base+KL_UART_RWFIFO_OFFSET); - + depth = g_sizemap[(regval & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT]; if (depth > 3) { depth = (depth >> 2); } putreg8(depth, uart_base+KL_UART_TWFIFO_OFFSET); - + /* Enable RX and TX FIFOs */ putreg8(UART_PFIFO_RXFE | UART_PFIFO_TXFE, uart_base+KL_UART_PFIFO_OFFSET); @@ -398,8 +393,8 @@ void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, * (1 in this case) is less than or equal to 0. * RWFIFO[RXWATER] = 1: RDRF will be set when the number of queued bytes * (1 in this case) is greater than or equal to 1. - * - * Set the watermarks to one/zero and disable the FIFOs + * + * Set the watermarks to one/zero and disable the FIFOs */ putreg8(1, uart_base+KL_UART_RWFIFO_OFFSET); diff --git a/nuttx/arch/arm/src/kl/kl_serial.c b/nuttx/arch/arm/src/kl/kl_serial.c index 6e4477c0b..b523965ea 100644 --- a/nuttx/arch/arm/src/kl/kl_serial.c +++ b/nuttx/arch/arm/src/kl/kl_serial.c @@ -69,11 +69,6 @@ * Pre-processor Definitions ****************************************************************************/ /* Some sanity checks *******************************************************/ - -#warning "Revisit" -#undef BOARD_CORECLK_FREQ -#define BOARD_CORECLK_FREQ 48000000 - /* Is there at least one UART enabled and configured as a RS-232 device? */ #ifndef HAVE_UART_DEVICE @@ -359,7 +354,7 @@ static uart_dev_t g_uart0port = static struct up_dev_s g_uart1priv = { .uartbase = KL_UART1_BASE, - .clock = BOARD_CORECLK_FREQ, + .clock = BOARD_BUSCLK_FREQ, .baud = CONFIG_UART1_BAUD, #ifdef CONFIG_DEBUG .irqe = KL_IRQ_UART1E, @@ -393,7 +388,7 @@ static uart_dev_t g_uart1port = static struct up_dev_s g_uart2priv = { .uartbase = KL_UART2_BASE, - .clock = BOARD_BUS_FREQ, + .clock = BOARD_BUSCLK_FREQ, .baud = CONFIG_UART2_BAUD, #ifdef CONFIG_DEBUG .irqe = KL_IRQ_UART2E, @@ -427,7 +422,7 @@ static uart_dev_t g_uart2port = static struct up_dev_s g_uart3priv = { .uartbase = KL_UART3_BASE, - .clock = BOARD_BUS_FREQ, + .clock = BOARD_BUSCLK_FREQ, .baud = CONFIG_UART3_BAUD, #ifdef CONFIG_DEBUG .irqe = KL_IRQ_UART3E, @@ -461,7 +456,7 @@ static uart_dev_t g_uart3port = static struct up_dev_s g_uart4priv = { .uartbase = KL_UART4_BASE, - .clock = BOARD_BUS_FREQ, + .clock = BOARD_BUSCLK_FREQ, .baud = CONFIG_UART4_BAUD, #ifdef CONFIG_DEBUG .irqe = KL_IRQ_UART4E, @@ -495,7 +490,7 @@ static uart_dev_t g_uart4port = static struct up_dev_s g_uart5priv = { .uartbase = KL_UART5_BASE, - .clock = BOARD_BUS_FREQ, + .clock = BOARD_BUSCLK_FREQ, .baud = CONFIG_UART5_BAUD, #ifdef CONFIG_DEBUG .irqe = KL_IRQ_UART5E, @@ -709,7 +704,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - + /* Disable interrupts */ up_restoreuartint(priv, 0); |