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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2010-10-11 02:56:03 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2010-10-11 02:56:03 +0000
commit1dd373e6fb99caad39b480069481e0ad676ca04f (patch)
treeabf29121e9bc33a359cd4e6e89f5ab27d407e48f /nuttx/arch/avr
parenta28333ebfc370e3229e7640853cab2a0ed16148d (diff)
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Add WDT header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2993 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/avr')
-rwxr-xr-xnuttx/arch/avr/src/at91uc3/at91uc3_wdt.h87
1 files changed, 87 insertions, 0 deletions
diff --git a/nuttx/arch/avr/src/at91uc3/at91uc3_wdt.h b/nuttx/arch/avr/src/at91uc3/at91uc3_wdt.h
new file mode 100755
index 000000000..46220e379
--- /dev/null
+++ b/nuttx/arch/avr/src/at91uc3/at91uc3_wdt.h
@@ -0,0 +1,87 @@
+/************************************************************************************
+ * arch/avr/src/at91uc3/at91uc3_wdt.h
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_AVR_SRC_AT91UC3_AT91UC3_WDT_H
+#define __ARCH_AVR_SRC_AT91UC3_AT91UC3_WDT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define AVR32_WDT_CTRL_OFFSET 0x00 /* Control Register */
+#define AVR32_WDT_CLR_OFFSET 0x04 /* Clear Register */
+
+/* Register Addresses ***************************************************************/
+
+#define AVR32_WDT_CTRL (AVR32_WDT_BASE+AVR32_WDT_CTRL_OFFSET)
+#define AVR32_WDT_CLR (AVR32_WDT_BASE+AVR32_WDT_CLR_OFFSET)
+
+/* Register Bit-field Definitions ***************************************************/
+
+/* Control Register Bit-field Definitions */
+
+#define WDT_CTRL_EN (1 << 0) /* Bit 0: WDT Enable */
+#define WDT_CTRL_PSEL_SHIFT (18) /* Bit 8-12: Prescale Select */
+#define WDT_CTRL_PSEL_MASK (0x1f << WDT_CTRL_PSEL_SHIFT)
+#define WDT_CTRL_KEY_SHIFT (24) /* Bits 24-31: Write protection key */
+#define WDT_CTRL_KEY_MASK (0xff << WDT_CTRL_KEY_SHIFT)
+
+/* Clear Register Bit-field Definitions. These register has no bit field: "Writing
+ * periodically any value to this field when the WDT is enabled, within the watchdog
+ * time-out period, will prevent a watchdog reset."
+ */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_AVR_SRC_AT91UC3_AT91UC3_WDT_H */
+