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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-02-17 23:21:28 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-02-17 23:21:28 +0000 |
commit | e3940eb2080711edac189cca3f642ee89dc215f2 (patch) | |
tree | 1c390958fae49e34dce698b175487e6d4681e540 /nuttx/arch/c5471/src/up_irq.c | |
parent | 2223612deb2cc6322992f8595b6d6f86fcb53ae1 (diff) | |
download | px4-nuttx-e3940eb2080711edac189cca3f642ee89dc215f2.tar.gz px4-nuttx-e3940eb2080711edac189cca3f642ee89dc215f2.tar.bz2 px4-nuttx-e3940eb2080711edac189cca3f642ee89dc215f2.zip |
NuttX RTOS
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/c5471/src/up_irq.c')
-rw-r--r-- | nuttx/arch/c5471/src/up_irq.c | 243 |
1 files changed, 243 insertions, 0 deletions
diff --git a/nuttx/arch/c5471/src/up_irq.c b/nuttx/arch/c5471/src/up_irq.c new file mode 100644 index 000000000..d388f6446 --- /dev/null +++ b/nuttx/arch/c5471/src/up_irq.c @@ -0,0 +1,243 @@ +/************************************************************ + * up_irq.c + * + * Copyright (C) 2007 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name Gregory Nutt nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************/ + +/************************************************************ + * Included Files + ************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> +#include <nuttx/irq.h> +#include "c5471.h" +#include "os_internal.h" +#include "up_internal.h" + +/************************************************************ + * Definitions + ************************************************************/ + +#define EdgeSensitive 0x00000020 +#define Priority 0x0000001E + +/************************************************************ + * Public Data + ************************************************************/ + +uint32 *current_regs; + +/************************************************************ + * Private Data + ************************************************************/ + +/* The value of _vflashstart is defined in ld.script. It + * could be hard-coded because we know that correct IRAM + * area is 0xffc00000. + */ + +extern int _svectors; /* Type does not matter */ + +/* The C5471 has FLASH at the low end of memory. The + * rrload bootloaer will catch all interrupts and re-vector + * them to vectors stored in IRAM. The following table is + * used to initialize those vectors. + */ + +static up_vector_t g_vectorinittab[] = +{ + (up_vector_t)NULL, + up_vectorundefinsn, + up_vectorswi, + up_vectorprefetch, + up_vectordata, + up_vectoraddrexcptn, + up_vectorirq, + up_vectorfiq +}; +#define NVECTORS ((sizeof(g_vectorinittab)) / sizeof(up_vector_t)) + +/************************************************************ + * Private Functions + ************************************************************/ + +/************************************************************ + * Name: up_ackirq + * + * Description: + * Acknowlede the IRQ.Bit 0 of the Interrupt Control + * Register == New IRQ agreement (NEW_IRQ_AGR). Reset IRQ + * output. Clear source IRQ register. Enables a new IRQ + * generation. Reset by internal logic. + * + ************************************************************/ + +static inline void up_ackirq(unsigned int irq) +{ + uint32 reg; + reg = getreg32(SRC_IRQ_REG); /* Insure appropriate IT_REG bit clears */ + putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */ +} + +/************************************************************ + * Name: up_ackfiq + * + * Description: + * Acknowledge the FIQ. Bit 1 of the Interrupt Control + * Register == New FIQ agreement (NEW_FIQ_AGR). Reset FIQ + * output. Clear source FIQ register. Enables a new FIQ + * generation. Reset by internal logic. + * + ************************************************************/ + +static inline void up_ackfiq(unsigned int irq) +{ + uint32 reg; + reg = getreg32(SRC_FIQ_REG); /* Insure appropriate IT_REG bit clears */ + putreg32(reg | 0x00000002, INT_CTRL_REG); /* write the NEW_FIQ_AGR bit. */ +} + +/************************************************************ + * Name: up_vectorinitialize + ************************************************************/ + +static inline void up_vectorinitialize(void) +{ + up_vector_t *src = g_vectorinittab; + up_vector_t *dest = (up_vector_t*)&_svectors; + int i; + for (i = 0; i < NVECTORS; i++) + { + *dest++ = *src++; + } +} + +/************************************************************ + * Public Funtions + ************************************************************/ + +/************************************************************ + * Name: irq_initialize + ************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable all interrupts. */ + + putreg32(0x0000ffff, MASK_IT_REG); + + /* Clear any pending interrupts */ + + up_ackirq(0); + up_ackfiq(0); + putreg32(0x00000000, IT_REG); + + /* Override hardware defaults */ + + putreg32(EdgeSensitive | Priority, ILR_IRQ2_REG); + putreg32(EdgeSensitive | Priority, ILR_IRQ4_REG); + putreg32(Priority, ILR_IRQ6_REG); + putreg32(EdgeSensitive | Priority, ILR_IRQ15_REG); + + /* Initialize hardware interrupt vectors */ + + up_vectorinitialize(); + current_regs = NULL; + + /* And finally, enable interrupts */ + + irqrestore(SVC_MODE | F_BIT); +} + +/************************************************************ + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ************************************************************/ + +void up_disable_irq(int irq) +{ + if (irq < NR_IRQS) + { + uint32 reg = getreg32(MASK_IT_REG); + putreg32(reg | (1 << irq), MASK_IT_REG); + } +} + +/************************************************************ + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ************************************************************/ + +void up_enable_irq(int irq) +{ + if (irq < NR_IRQS) + { + uint32 reg = getreg32(MASK_IT_REG); + putreg32(reg & ~(1 << irq), MASK_IT_REG); + } +} + +/************************************************************ + * Name: up_acknowledge_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ************************************************************/ + +/* Bit 0 of the Interrupt Control Rigster == New IRQ + * agreement (NEW_IRQ_AGR). Reset IRQ output. Clear source + * IRQ register. Enables a new IRQ generation. Reset by + * internal logic. + * + * IRQ (FIQ) output and SRC_IRQ_REG and SRC_IRQ_BIN_REG + * (SRC_FIQ_REG) registers are reset only if the bit in the + * Interrupt register (IT_REG) corresponding to the interrupt + * having requested MCU action is already cleared or masked. + * + * For an edge-sensitive interrupt, the Interrupt register bit is + * deactivated when reading the SRC_IRQ_REG or SRC_IRQ_BIN_REG + * (SRC_FIQ_REG) registers. + */ + +void up_acknowledge_irq(int irq) +{ + uint32 reg = getreg32(INT_CTRL_REG); + putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */ +} |