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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-12-11 21:55:37 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-12-11 21:55:37 +0000 |
| commit | 85e0e91f408ee6c26e6eeb07742a73d3871215ce (patch) | |
| tree | 602367f4ce80060ed8e6465cfa1c237b57725105 /nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h | |
| parent | d8ac0a01d815d109e177b6f752806f8512c4319e (diff) | |
| download | px4-nuttx-85e0e91f408ee6c26e6eeb07742a73d3871215ce.tar.gz px4-nuttx-85e0e91f408ee6c26e6eeb07742a73d3871215ce.tar.bz2 px4-nuttx-85e0e91f408ee6c26e6eeb07742a73d3871215ce.zip | |
Flash layout, bootloader, paging fixes
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2321 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h')
| -rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h index 3731621fb..cd4794fc2 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h @@ -50,33 +50,33 @@ /* CRG Module Register Offsets */
-#define HCS12_CRG_SYNR_OFFSET 0x34 /* CRG Synthesizer Register */
-#define HCS12_CRG_REFDV_OFFSET 0x35 /* CRG Reference Divider Register */
-#define HCS12_CRG_CTFLG_OFFSET 0x36 /* CRG Test Flags Register */
-#define HCS12_CRG_CRGFLG_OFFSET 0x37 /* CRG Flags Register */
-#define HCS12_CRG_CRGINT_OFFSET 0x38 /* CRG Interrupt Enable Register */
-#define HCS12_CRG_CLKSEL_OFFSET 0x39 /* CRG Clock Select Register */
-#define HCS12_CRG_PLLCTL_OFFSET 0x3a /* CRG PLL Control Register */
-#define HCS12_CRG_RTICTL_OFFSET 0x3b /* CRG RTI Control Register */
-#define HCS12_CRG_COPCTL_OFFSET 0x3c /* CRG COP Control Register */
-#define HCS12_CRG_FORBYP_OFFSET 0x3d /* CRG Force and Bypass Test Register */
-#define HCS12_CRG_CTCTL_OFFSET 0x3e /* CRG Test Control Register */
-#define HCS12_CRG_ARMCOP_OFFSET 0x3f /* CRG COP Arm/Timer Reset */
+#define HCS12_CRG_SYNR_OFFSET (HCS12_CRG_BASE+0x00) /* CRG Synthesizer Register */
+#define HCS12_CRG_REFDV_OFFSET (HCS12_CRG_BASE+0x01) /* CRG Reference Divider Register */
+#define HCS12_CRG_CTFLG_OFFSET (HCS12_CRG_BASE+0x02) /* CRG Test Flags Register */
+#define HCS12_CRG_CRGFLG_OFFSET (HCS12_CRG_BASE+0x03) /* CRG Flags Register */
+#define HCS12_CRG_CRGINT_OFFSET (HCS12_CRG_BASE+0x04) /* CRG Interrupt Enable Register */
+#define HCS12_CRG_CLKSEL_OFFSET (HCS12_CRG_BASE+0x05) /* CRG Clock Select Register */
+#define HCS12_CRG_PLLCTL_OFFSET (HCS12_CRG_BASE+0x06) /* CRG PLL Control Register */
+#define HCS12_CRG_RTICTL_OFFSET (HCS12_CRG_BASE+0x07) /* CRG RTI Control Register */
+#define HCS12_CRG_COPCTL_OFFSET (HCS12_CRG_BASE+0x08) /* CRG COP Control Register */
+#define HCS12_CRG_FORBYP_OFFSET (HCS12_CRG_BASE+0x09) /* CRG Force and Bypass Test Register */
+#define HCS12_CRG_CTCTL_OFFSET (HCS12_CRG_BASE+0x0a) /* CRG Test Control Register */
+#define HCS12_CRG_ARMCOP_OFFSET (HCS12_CRG_BASE+0x0b) /* CRG COP Arm/Timer Reset */
/* CRG Module Register Addresses */
-#define HCS12_CRG_SYNR (HCS12_MODULE_BASE+HCS12_CRG_SYNR_OFFSET)
-#define HCS12_CRG_REFDV (HCS12_MODULE_BASE+HCS12_CRG_REFDV_OFFSET)
-#define HCS12_CRG_CTFLG (HCS12_MODULE_BASE+HCS12_CRG_CTFLG_OFFSET)
-#define HCS12_CRG_CRGFLG (HCS12_MODULE_BASE+HCS12_CRG_CRGFLG_OFFSET)
-#define HCS12_CRG_CRGINT (HCS12_MODULE_BASE+HCS12_CRG_CRGINT_OFFSET)
-#define HCS12_CRG_CLKSEL (HCS12_MODULE_BASE+HCS12_CRG_CLKSEL_OFFSET)
-#define HCS12_CRG_PLLCTL (HCS12_MODULE_BASE+HCS12_CRG_PLLCTL_OFFSET)
-#define HCS12_CRG_RTICTL (HCS12_MODULE_BASE+HCS12_CRG_RTICTL_OFFSET)
-#define HCS12_CRG_COPCTL (HCS12_MODULE_BASE+HCS12_CRG_COPCTL_OFFSET)
-#define HCS12_CRG_FORBYP (HCS12_MODULE_BASE+HCS12_CRG_FORBYP_OFFSET)
-#define HCS12_CRG_CTCTL (HCS12_MODULE_BASE+HCS12_CRG_CTCTL_OFFSET)
-#define HCS12_CRG_ARMCOP (HCS12_MODULE_BASE+HCS12_CRG_ARMCOP_OFFSET)
+#define HCS12_CRG_SYNR (HCS12_REG_BASE+HCS12_CRG_SYNR_OFFSET)
+#define HCS12_CRG_REFDV (HCS12_REG_BASE+HCS12_CRG_REFDV_OFFSET)
+#define HCS12_CRG_CTFLG (HCS12_REG_BASE+HCS12_CRG_CTFLG_OFFSET)
+#define HCS12_CRG_CRGFLG (HCS12_REG_BASE+HCS12_CRG_CRGFLG_OFFSET)
+#define HCS12_CRG_CRGINT (HCS12_REG_BASE+HCS12_CRG_CRGINT_OFFSET)
+#define HCS12_CRG_CLKSEL (HCS12_REG_BASE+HCS12_CRG_CLKSEL_OFFSET)
+#define HCS12_CRG_PLLCTL (HCS12_REG_BASE+HCS12_CRG_PLLCTL_OFFSET)
+#define HCS12_CRG_RTICTL (HCS12_REG_BASE+HCS12_CRG_RTICTL_OFFSET)
+#define HCS12_CRG_COPCTL (HCS12_REG_BASE+HCS12_CRG_COPCTL_OFFSET)
+#define HCS12_CRG_FORBYP (HCS12_REG_BASE+HCS12_CRG_FORBYP_OFFSET)
+#define HCS12_CRG_CTCTL (HCS12_REG_BASE+HCS12_CRG_CTCTL_OFFSET)
+#define HCS12_CRG_ARMCOP (HCS12_REG_BASE+HCS12_CRG_ARMCOP_OFFSET)
/* CRG Module Register Bit Definitions */
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