Add PIC32 interrupt controls and timer initialization

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3628 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 256 insertions, 8 deletions

diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
index 19ecfb8e7..3d7d363bc 100755
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
@@ -53,6 +53,8 @@
 #include "up_arch.h"
 #include "os_internal.h"
 #include "up_internal.h"
+
+#include "pic32mx-int.h"
 #include "pic32mx-internal.h"
 
 /****************************************************************************
@@ -83,14 +85,43 @@ volatile uint32_t *current_regs;
 
 void up_irqinitialize(void)
 {
+  uint32_t regval;
+  int irq;
+
   /* Disable all interrupts */
-#warning "Missing logic"
+
+  putreg32(0xffff, PIC32MX_INT_IEC0CLR);
+  putreg32(0xffff, PIC32MX_INT_IEC1CLR);
+
+  /* Set all interrupts to the default (middle) priority */
+
+  for (irq = 0; irq < NR_IRQS; irq++)
+    {
+      (void)up_prioritize_irq(irq, (INT_CP0_MID_PRIORITY << 2));
+    }
+  
+  /* Set the CP0 cause IV bit meaning that the interrupt exception uses
+   * the "special interrupt vector"
+   */
+ 
+  asm volatile("\tmfc0 %0,$13,0\n" : "=r"(regval));
+  regval |= CP0_CAUSE_IV; 
+  asm volatile("\tmtc0 %0,$13,0\n" : : "r"(regval));
+
+  /* Configure multi- or single- vector interrupts */
+
+#ifdef CONFIG_PIC32MX_MVEC
+  putreg32(INT_INTCON_MVEC, PIC32MX_INT_INTCONSET);
+#else
+  putreg32(INT_INTCON_MVEC, PIC32MX_INT_INTCONCLR);
+#endif
 
   /* currents_regs is non-NULL only while processing an interrupt */
 
   current_regs = NULL;
 
   /* Attach processor exceptions */
+#warning "Missing logic"
 
   /* Initialize logic to support a second level of interrupt decoding for
    * IOPORT pins.
@@ -103,6 +134,14 @@ void up_irqinitialize(void)
   /* And finally, enable interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+  /* Interrupts are enabled by setting the IE bit in the CP0 status register */
+
+  regval = 0;
+  asm volatile("ei    %0" : "=r"(regval));
+
+  /* Then enable all interrupt levels */
+
   irqrestore(CP0_STATUS_IM_ALL);
 #endif
 }
@@ -117,7 +156,39 @@ void up_irqinitialize(void)
 
 void up_disable_irq(int irq)
 {
-#warning "Missing logic"
+  uint32_t regaddr;
+  int bitno;
+
+  /* Disable the interrupt by clearing the associated bit in the IEC register */
+
+  DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
+  if (irq >= PIC32MX_IRQSRC0_FIRST)
+    {
+      if (irq <= PIC32MX_IRQSRC0_LAST)
+        {
+          /* Use IEC0 */
+
+          regaddr = PIC32MX_INT_IEC0CLR;
+          bitno  -= PIC32MX_IRQSRC0_FIRST;
+        }
+      else if (irq <= PIC32MX_IRQSRC1_LAST)
+        {
+          /* Use IEC1 */
+
+          regaddr = PIC32MX_INT_IEC1CLR;
+          bitno  -= PIC32MX_IRQSRC1_FIRST;
+        }
+      else
+        {
+          /* Value out of range.. just ignore */
+
+          return;
+        }
+
+      /* Disable the interrupt */
+
+      putreg32((1 << bitno), regaddr);
+    }
 }
 
 /****************************************************************************
@@ -130,24 +201,201 @@ void up_disable_irq(int irq)
 
 void up_enable_irq(int irq)
 {
-#warning "Missing logic"
+  uint32_t regaddr;
+  int bitno;
+
+  /* Enable the interrupt by setting the associated bit in the IEC register */
+
+  DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
+  if (irq >= PIC32MX_IRQSRC0_FIRST)
+    {
+      if (irq <= PIC32MX_IRQSRC0_LAST)
+        {
+          /* Use IEC0 */
+
+          regaddr = PIC32MX_INT_IEC0SET;
+          bitno  -= PIC32MX_IRQSRC0_FIRST;
+        }
+      else if (irq <= PIC32MX_IRQSRC1_LAST)
+        {
+          /* Use IEC1 */
+
+          regaddr = PIC32MX_INT_IEC1SET;
+          bitno  -= PIC32MX_IRQSRC1_FIRST;
+        }
+      else
+        {
+          /* Value out of range.. just ignore */
+
+          return;
+        }
+
+      /* Disable the interrupt */
+
+      putreg32((1 << bitno), regaddr);
+    }
+}
+
+/****************************************************************************
+ * Name: up_clrpend_irq
+ *
+ * Description:
+ *   Clear any pending interrupt
+ *
+ ****************************************************************************/
+
+void up_clrpend_irq(int irq)
+{
+  uint32_t regaddr;
+  int bitno;
+
+  /* Disable the interrupt by clearing the associated bit in the IEC and then
+   * acknowledge the interrupt by clearing the associated bit in the IFS
+   * register.  It is necessary to do this BEFORE lowering the interrupt
+   * priority level otherwise recursive interrupts would occur.
+   */
+
+  DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
+  if (irq >= PIC32MX_IRQSRC0_FIRST)
+    {
+      if (irq <= PIC32MX_IRQSRC0_LAST)
+        {
+          /* Use IFS0 */
+
+          regaddr = PIC32MX_INT_IFS0CLR;
+          bitno  -= PIC32MX_IRQSRC0_FIRST;
+        }
+      else if (irq <= PIC32MX_IRQSRC1_LAST)
+        {
+          /* Use IFS1 */
+
+          regaddr = PIC32MX_INT_IFS1CLR;
+          bitno  -= PIC32MX_IRQSRC1_FIRST;
+        }
+      else
+        {
+          /* Value out of range.. just ignore */
+
+          return;
+        }
+
+      /* Disable then acknowledge interrupt */
+
+      putreg32((1 << bitno), regaddr);
+    }
+}
+
+/****************************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it.  This could be done by calling
+ *   up_disable_irq followed by up_clrpend_irq, but since these function is
+ *   called from interrupt handling logic it is probably worth the improved
+ *   performance by doing doing both here.
+ *
+ ****************************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  uint32_t iecaddr;
+  uint32_t ifsaddr;
+  int bitno;
+
+  /* Disable the interrupt by clearing the associated bit in the IEC and then
+   * acknowledge the interrupt by clearing the associated bit in the IFS
+   * register.  It is necessary to do this BEFORE lowering the interrupt
+   * priority level otherwise recursive interrupts would occur.
+   */
+
+  DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
+  if (irq >= PIC32MX_IRQSRC0_FIRST)
+    {
+      if (irq <= PIC32MX_IRQSRC0_LAST)
+        {
+          /* Use IEC0 and IFS0*/
+
+          iecaddr = PIC32MX_INT_IEC0CLR;
+          ifsaddr = PIC32MX_INT_IFS0CLR;
+          bitno  -= PIC32MX_IRQSRC0_FIRST;
+        }
+      else if (irq <= PIC32MX_IRQSRC1_LAST)
+        {
+          /* Use IEC1 and IFS1 */
+
+          iecaddr = PIC32MX_INT_IEC1CLR;
+          ifsaddr = PIC32MX_INT_IFS1CLR;
+          bitno  -= PIC32MX_IRQSRC1_FIRST;
+        }
+      else
+        {
+          /* Value out of range.. just ignore */
+
+          return;
+        }
+
+      /* Disable then acknowledge interrupt */
+
+      putreg32((1 << bitno), iecaddr);
+      putreg32((1 << bitno), ifsaddr);
+    }
 }
 
 /****************************************************************************
  * Name: up_prioritize_irq
  *
  * Description:
- *   Set the priority of an IRQ.
+ *   Set the priority of an IRQ by setting the priority and sub-priority
+ *   fields in the PIC32MX IPC registers.  There are 12 IPC registers, IPC0
+ *   through IPC11.  Each has sub-priority fields for 8 interrupts for a
+ *   total of 96 interrupts max.
+ *
+ *   Each interrupt priority is represent by a group of 5 bits: a 3-bit
+ *   priority and a 2-bit sub-priority.  These have different meanings to
+ *   the hardware.  The priority is the priority level that is enabled
+ *   or masked by the IPL field of the CAUSE register.  The sub-priority
+ *   only mediates ties when two interrupts with the same priority pend
+ *   simultaneously.
+ *
+ *   In this function, we just treat this as a single 5-bit priority.
+ *   (MS 3-bits=priority; LS 2-bits=sub-priority).
  *
- *   Since this API is not supported on all architectures, it should be
- *   avoided in common implementations where possible.
+ *   The 5-bit priority/sub-priority fields are arranged at byte boundaries
+ *   within each IPC register:
+ *
+ *     xxxP PPSS xxxP PPSS xxxP PPSS xxxP PPSS
  *
  ****************************************************************************/
 
 #ifdef CONFIG_ARCH_IRQPRIO
 int up_prioritize_irq(int irq, int priority)
 {
-#warning "Missing logic"
-  return -ENOSYS;
+  int regndx;
+  int shift;
+
+  /* Don't allow this function to be used for disabling interrupts.  There is
+   * no good reason for this restriction other than I want to make sure that
+   * the 5-bit priority values passed to this function are *not* confused with
+   * the 3-bit hardware priority values.
+   */
+
+  DEBUGASSERT((unsigned)irq < NR_IRQS && (unsigned)(priority >> 2) > 0);
+  if (irq < NR_IRQS)
+    {
+      /* Get the index to the IPC register and the shift to the 5-bit priority
+       * field for this IRQ.
+       */
+
+      regndx = irq >> 2;       /* Range: 0-11 */
+      shift  = (irq & 3) << 3; /* {0, 8, 16, 24 } */
+
+      /* Set the new interrupt priority (momentarily disabling interrupts) */
+
+      putreg32(0x1f << shift, PIC32MX_INT_IPCCLR(regndx));
+      putreg32(priority << shift, PIC32MX_INT_IPCSET(regndx));
+      return OK;
+    }
+
+  return -EINVAL;
 }
 #endif