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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2012-06-06 01:44:57 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2012-06-06 01:44:57 +0000
commit7b6936598c0f53b68c26ac827d2d33e89c52c2b5 (patch)
treee47988218982531e9c9d129ce3170d7efe1a3534 /nuttx/arch/mips
parent8542f3ce1b6c90106d4c113cd708996b937654a2 (diff)
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Fix a bad interrupt state in the PIC32 IDLE loop when the work queue is enabled
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4805 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/mips')
-rw-r--r--nuttx/arch/mips/src/common/up_idle.c24
-rw-r--r--nuttx/arch/mips/src/mips32/up_initialstate.c2
-rw-r--r--nuttx/arch/mips/src/mips32/up_irq.c2
3 files changed, 23 insertions, 5 deletions
diff --git a/nuttx/arch/mips/src/common/up_idle.c b/nuttx/arch/mips/src/common/up_idle.c
index 239aa3c30..4e2cc542b 100644
--- a/nuttx/arch/mips/src/common/up_idle.c
+++ b/nuttx/arch/mips/src/common/up_idle.c
@@ -1,8 +1,8 @@
/****************************************************************************
* arch/mips/src/common/up_idle.c
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -81,9 +81,27 @@ void up_idle(void)
sched_process_timer();
#else
- /* This would be an appropriate place to put some MCU-specific logig to
+ /* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
+
+ /* This is a kludge that I still don't understand. The call to kmm_trysemaphore()
+ * in the os_start.c IDLE loop seems necessary for the good health of the IDLE
+ * loop. When the work queue is enabled, this logic is removed from the IDLE
+ * loop and it appears that we are somehow left idling with interrupts non-
+ * functional. The following should be no-op, it just disables then re-enables
+ * interrupts. But it fixes the problem and will stay here until I understand
+ * the problem/fix better.
+ *
+ * And no, the contents of the CP0 status register are not incorrect. But for
+ * some reason the status register needs to be re-written again on this thread
+ * for it to take effect. This might be a PIC32-only issue?
+ */
+
+#ifdef CONFIG_SCHED_WORKQUEUE
+ irqstate_t flags = irqsave();
+ irqrestore(flags);
+#endif
#endif
}
diff --git a/nuttx/arch/mips/src/mips32/up_initialstate.c b/nuttx/arch/mips/src/mips32/up_initialstate.c
index cc0cd227e..0c24d1ee0 100644
--- a/nuttx/arch/mips/src/mips32/up_initialstate.c
+++ b/nuttx/arch/mips/src/mips32/up_initialstate.c
@@ -2,7 +2,7 @@
* arch/mips/src/mips32/up_initialstate.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ * Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/nuttx/arch/mips/src/mips32/up_irq.c b/nuttx/arch/mips/src/mips32/up_irq.c
index 80ab7f78a..b13ae6294 100644
--- a/nuttx/arch/mips/src/mips32/up_irq.c
+++ b/nuttx/arch/mips/src/mips32/up_irq.c
@@ -2,7 +2,7 @@
* arch/mips/src/mips32/up_irq.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ * Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions