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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-04-07 13:46:05 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-04-07 13:46:05 -0600 |
| commit | 144f80ab044da641c8060c28fe5b4ea4c7e7fb07 (patch) | |
| tree | 0c728e15214d9a8c9261ad6162051a19a126895f /nuttx/arch | |
| parent | 9f0c540dc984183b3b5a5753efb43f3ee504e32b (diff) | |
| download | px4-nuttx-144f80ab044da641c8060c28fe5b4ea4c7e7fb07.tar.gz px4-nuttx-144f80ab044da641c8060c28fe5b4ea4c7e7fb07.tar.bz2 px4-nuttx-144f80ab044da641c8060c28fe5b4ea4c7e7fb07.zip | |
LPC17xx GPIO interrupt fixes: lpc17_setintedge() must be atomic. Can't disable interrupts from interrupt handlers because they are automatically re-enabled. Try re-configuring pin instead.
Diffstat (limited to 'nuttx/arch')
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c | 13 |
2 files changed, 11 insertions, 4 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h index 170d9ceee..be749e8c4 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h @@ -99,7 +99,7 @@ #define GPIO_SSP1_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_MAT2p2_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_RTC_EV1_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_LCD_VD16 (GPIO_ALT7 | GPIO_FLOA | GPIO_HYSTERESIST | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_LCD_VD16 (GPIO_ALT7 | GPIO_FLOAT | GPIO_HYSTERESIS | GPIO_PORT0 | GPIO_PIN8) #define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) #define GPIO_SSP1_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c index a8e4bd641..1d6b4b1d6 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c @@ -116,8 +116,13 @@ static unsigned int lpc17_getintedge(unsigned int port, unsigned int pin) static void lpc17_setintedge(uint32_t intbase, unsigned int pin, unsigned int edges) { + irqstate_t flags; int regval; + /* These must be atomic */ + + flags = irqsave(); + /* Set/clear the rising edge enable bit */ regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); @@ -145,6 +150,7 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin, } putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET); + irqrestore(flags); } /**************************************************************************** @@ -389,9 +395,10 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, * Name: lpc17_gpiointerrupt * * Description: - * Handle the EINT3 interrupt that also indicates that a GPIO interrupt has - * occurred. NOTE: This logic will have to be extended if EINT3 is - * actually used for External Interrupt 3. + * Handle the GPIO interrupt. For the LPC176x family, that interrupt could + * also that also indicates that an EINT3 interrupt has occurred. NOTE: + * This logic would have to be extended if EINT3 is actually used for + * External Interrupt 3 on an LPC176x platform. * ****************************************************************************/ |