SAMA5: Back out most of commit c37b5b7b97d0644743c04f2c3d9e2b7ef9f5d698. Things are going to have to be done differently

11 files changed, 505 insertions, 303 deletions

diff --git a/nuttx/arch/arm/src/sama5/Kconfig b/nuttx/arch/arm/src/sama5/Kconfig
index e169c595b..7a21f3dfe 100644
--- a/nuttx/arch/arm/src/sama5/Kconfig
+++ b/nuttx/arch/arm/src/sama5/Kconfig
@@ -61,6 +61,10 @@ config SAMA5_HAVE_GMAC
 	bool
 	default n
 
+config SAMA5_HAVE_EMAC
+	bool
+	default n
+
 config SAMA5_HAVE_EMAC0
 	bool
 	default n
@@ -141,7 +145,7 @@ choice
 config ARCH_CHIP_ATSAMA5D31
 	bool "Atmel ATSAMA5D31"
 	select ARCH_CHIP_SAMA5D3
-	select SAMA5_HAVE_EMAC0
+	select SAMA5_HAVE_EMAC
 	select SAMA5_HAVE_HSMCI2
 	select SAMA5_HAVE_LCDC
 	select SAMA5_HAVE_UART0
@@ -168,7 +172,7 @@ config ARCH_CHIP_ATSAMA5D34
 config ARCH_CHIP_ATSAMA5D35
 	bool "Atmel ATSAMA5D35"
 	select ARCH_CHIP_SAMA5D3
-	select SAMA5_HAVE_EMAC0
+	select SAMA5_HAVE_EMAC
 	select SAMA5_HAVE_GMAC
 	select SAMA5_HAVE_HSMCI2
 	select SAMA5_HAVE_UART0
@@ -181,7 +185,7 @@ config ARCH_CHIP_ATSAMA5D35
 config ARCH_CHIP_ATSAMA5D36
 	bool "Atmel ATSAMA5D356"
 	select ARCH_CHIP_SAMA5D3
-	select SAMA5_HAVE_EMAC0
+	select SAMA5_HAVE_EMAC
 	select SAMA5_HAVE_GMAC
 	select SAMA5_HAVE_HSMCI2
 	select SAMA5_HAVE_LCDC
@@ -418,6 +422,13 @@ config SAMA5_GMAC
 	select NETDEVICES
 	select ARCH_HAVE_PHY
 
+config SAMA5_EMAC
+	bool "10/100MBps Ethernet MAC (EMAC0)"
+	default n
+	depends on SAMA5_HAVE_EMAC
+	select NETDEVICES
+	select ARCH_HAVE_PHY
+
 config SAMA5_EMAC0
 	bool "10/100MBps Ethernet MAC (EMAC0)"
 	default n
@@ -1146,6 +1157,185 @@ config SAMA5_GMAC_REGDEBUG
 endmenu # GMAC device driver options
 endif # SAMA5_GMAC
 
+if SAMA5_EMAC
+
+menu "EMAC device driver options"
+
+config SAMA5_EMAC_NRXBUFFERS
+	int "Number of RX buffers"
+	default 16
+	---help---
+		EMAC buffer memory is segmented into 128 byte units (not
+		configurable).  This setting provides the number of such 128 byte
+		units used for reception.  This is also equal to the number of RX
+		descriptors that will be allocated  The selected value must be an
+		even power of 2.
+
+config SAMA5_EMAC_NTXBUFFERS
+	int "Number of TX buffers"
+	default 8
+	---help---
+		EMAC buffer memory is segmented into full Ethernet packets (size
+		NET_BUFSIZE bytes).  This setting provides the number of such packets
+		that can be in flight.  This is also equal to the number of TX
+		descriptors that will be allocated.
+
+config SAMA5_EMAC_PREALLOCATE
+	bool "Preallocate buffers"
+	default n
+	---help---
+		Buffer an descriptor many may either be allocated from the memory
+		pool or pre-allocated to lie in .bss.  This options selected pre-
+		allocated buffer memory.
+
+config SAMA5_EMAC_NBC
+	bool "Disable Broadcast"
+	default n
+	---help---
+		Select to disable receipt of broadcast packets.
+
+config SAMA5_EMAC_PHYADDR
+	int "PHY address"
+	default 1
+	---help---
+		The 5-bit address of the PHY on the board.  Default: 1
+
+config SAMA5_EMAC_PHYINIT
+	bool "Board-specific PHY Initialization"
+	default n
+	---help---
+		Some boards require specialized initialization of the PHY before it can be used.
+		This may include such things as configuring GPIOs, resetting the PHY, etc.  If
+		SAMA5_EMAC_PHYINIT is defined in the configuration then the board specific logic must
+		provide sam_phyinitialize();  The SAMA5 EMAC driver will call this function
+		one time before it first uses the PHY.
+
+config SAMA5_EMAC_MII
+	bool "Use MII interface"
+	default n
+	---help---
+		Support Ethernet MII interface (vs RMII).
+
+config SAMA5_EMAC_RMII
+	bool
+	default y if !SAMA5_EMAC_MII
+	default n if SAMA5_EMAC_MII
+
+config SAMA5_EMAC_AUTONEG
+	bool "Use autonegotiation"
+	default y
+	---help---
+		Use PHY autonegotiation to determine speed and mode
+
+config SAMA5_EMAC_ETHFD
+	bool "Full duplex"
+	default n
+	depends on !SAMA5_EMAC_AUTONEG
+	---help---
+		If SAMA5_EMAC_AUTONEG is not defined, then this may be defined to select full duplex
+		mode. Default: half-duplex
+
+config SAMA5_EMAC_ETH100MBPS
+	bool "100 Mbps"
+	default n
+	depends on !SAMA5_EMAC_AUTONEG
+	---help---
+		If SAMA5_EMAC_AUTONEG is not defined, then this may be defined to select 100 MBps
+		speed.  Default: 10 Mbps
+
+config SAMA5_EMAC_PHYSR
+	int "PHY Status Register Address (decimal)"
+	depends on SAMA5_EMAC_AUTONEG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  The PHY status register
+		address may diff from PHY to PHY.  This configuration sets the address of
+		the PHY status register.
+
+config SAMA5_EMAC_PHYSR_ALTCONFIG
+	bool "PHY Status Alternate Bit Layout"
+	default n
+	depends on SAMA5_EMAC_AUTONEG
+	---help---
+		Different PHYs present speed and mode information in different ways.  Some
+		will present separate information for speed and mode (this is the default).
+		Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
+		full/half duplex indication. This options selects an alternative representation
+		where speed and mode information are combined.  This might mean, for example,
+		separate bits for 10HD, 100HD, 10FD and 100FD.
+
+config SAMA5_EMAC_PHYSR_SPEED
+	hex "PHY Speed Mask"
+	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provides bit mask
+		for isolating the 10 or 100MBps speed indication.
+
+config SAMA5_EMAC_PHYSR_100MBPS
+	hex "PHY 100Mbps Speed Value"
+	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provides the value
+		of the speed bit(s) indicating 100MBps speed.
+
+config SAMA5_EMAC_PHYSR_MODE
+	hex "PHY Mode Mask"
+	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provide bit mask
+		for isolating the full or half duplex mode bits.
+
+config SAMA5_EMAC_PHYSR_FULLDUPLEX
+	hex "PHY Full Duplex Mode Value"
+	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provides the
+		value of the mode bits indicating full duplex mode.
+
+config SAMA5_EMAC_PHYSR_ALTMODE
+	hex "PHY Mode Mask"
+	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provide bit mask
+		for isolating the speed and full/half duplex mode bits.
+
+config SAMA5_EMAC_PHYSR_10HD
+	hex "10MBase-T Half Duplex Value"
+	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 10Mbps, half duplex setting.
+
+config SAMA5_EMAC_PHYSR_100HD
+	hex "100Base-T Half Duplex Value"
+	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 100Mbps, half duplex setting.
+
+config SAMA5_EMAC_PHYSR_10FD
+	hex "10Base-T Full Duplex Value"
+	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 10Mbps, full duplex setting.
+
+config SAMA5_EMAC_PHYSR_100FD
+	hex "100Base-T Full Duplex Value"
+	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 100Mbps, full duplex setting.
+
+config SAMA5_EMAC_REGDEBUG
+	bool "Register-Level Debug"
+	default n
+	depends on DEBUG
+	---help---
+		Enable very low-level register access debug.  Depends on DEBUG.
+
+endmenu # EMAC device driver options
+endif # SAMA5_EMAC
+
 if SAMA5_EMAC0
 
 menu "EMAC0 device driver options"
@@ -1199,16 +1389,43 @@ config SAMA5_EMAC0_PHYINIT
 		provide sam_phyinitialize();  The SAMA5 EMAC driver will call this function
 		one time before it first uses the PHY.
 
+choice
+	prompt "PHY interface"
+	default SAMA5_EMAC0_MII
+
 config SAMA5_EMAC0_MII
-	bool "Use MII interface"
-	default n
+	bool "MII"
 	---help---
 		Support Ethernet MII interface (vs RMII).
 
 config SAMA5_EMAC0_RMII
-	bool
-	default y if !SAMA5_EMAC0_MII
-	default n if SAMA5_EMAC0_MII
+	bool "RMII"
+	depends on !ARCH_CHIP_SAM4E
+	---help---
+		Support Ethernet RMII interface (vs MII).
+
+endchoice # PHY interface
+
+config SAMA5_EMAC0_CLAUSE45
+	bool "Clause 45 MII"
+	depends on SAMA5_EMAC0_MII
+	---help---
+		MDIO was originally defined in Clause 22 of IEEE RFC802.3. In the
+		original specification, a single MDIO interface is able to access up
+		to 32 registers in 32 different PHY devices.  To meet the needs the
+		expanding needs of 10-Gigabit Ethernet devices, Clause 45 of the
+		802.3ae specification provided the following additions to MDIO:
+
+		- Ability to access 65,536 registers in 32 different devices on
+		  32 different ports
+		- Additional OP-code and ST-code for Indirect Address register
+		  access for 10 Gigabit Ethernet
+		- End-to-end fault signaling
+		- Multiple loopback points
+		- Low voltage electrical specification
+
+		By default, Clause 22 PHYs will be supported unless this option is
+		selected.
 
 config SAMA5_EMAC0_AUTONEG
 	bool "Use autonegotiation"
@@ -1378,16 +1595,43 @@ config SAMA5_EMAC1_PHYINIT
 		provide sam_phyinitialize();  The SAMA5 EMAC driver will call this function
 		one time before it first uses the PHY.
 
+choice
+	prompt "PHY interface"
+	default SAMA5_EMAC1_MII
+
 config SAMA5_EMAC1_MII
-	bool "Use MII interface"
-	default n
+	bool "MII"
 	---help---
 		Support Ethernet MII interface (vs RMII).
 
 config SAMA5_EMAC1_RMII
-	bool
-	default y if !SAMA5_EMAC1_MII
-	default n if SAMA5_EMAC1_MII
+	bool "RMII"
+	depends on !ARCH_CHIP_SAM4E
+	---help---
+		Support Ethernet RMII interface (vs MII).
+
+endchoice # PHY interface
+
+config SAMA5_EMAC1_CLAUSE45
+	bool "Clause 45 MII"
+	depends on SAMA5_EMAC1_MII
+	---help---
+		MDIO was originally defined in Clause 22 of IEEE RFC802.3. In the
+		original specification, a single MDIO interface is able to access up
+		to 32 registers in 32 different PHY devices.  To meet the needs the
+		expanding needs of 10-Gigabit Ethernet devices, Clause 45 of the
+		802.3ae specification provided the following additions to MDIO:
+
+		- Ability to access 65,536 registers in 32 different devices on
+		  32 different ports
+		- Additional OP-code and ST-code for Indirect Address register
+		  access for 10 Gigabit Ethernet
+		- End-to-end fault signaling
+		- Multiple loopback points
+		- Low voltage electrical specification
+
+		By default, Clause 22 PHYs will be supported unless this option is
+		selected.
 
 config SAMA5_EMAC1_AUTONEG
 	bool "Use autonegotiation"
@@ -1504,12 +1748,17 @@ config SAMA5_EMAC1_REGDEBUG
 endmenu # EMAC1 device driver options
 endif # SAMA5_EMAC1
 
-if SAMA5_EMAC0 || SAMA5_EMAC1 || SAMA5_GMAC
+if SAMA5_EMAC || SAMA5_EMAC0 || SAMA5_EMAC1 || SAMA5_GMAC
 choice
 	prompt "Which device is eth0"
 	default SAMA5_GMAC_ISETH0 if SAMA5_GMAC
-	default SAMA5_EMAC0_ISETH0 if SAMA5_EMAC0 && !SAMA5_GMAC
-	default SAMA5_EMAC1_ISETH0 if SAMA5_EMAC1 && !SAMA5_EMAC0 && !SAMA5_GMAC
+	default SAMA5_EMAC_ISETH0 if SAMA5_EMAC && !SAMA5_GMAC
+	default SAMA5_EMAC0_ISETH0 if SAMA5_EMAC0 && !SAM_EMAC && !SAMA5_GMAC
+	default SAMA5_EMAC1_ISETH0 if SAMA5_EMAC1 && !SAM_EMAC && !SAMA5_EMAC0 && !SAMA5_GMAC
+
+config SAMA5_EMAC_ISETH0
+	bool "EMAC is eth0"
+	depends on SAMA5_EMAC
 
 config SAMA5_EMAC0_ISETH0
 	bool "EMAC0 is eth0"
@@ -1524,7 +1773,7 @@ config SAMA5_GMAC_ISETH0
 	depends on SAMA5_GMAC
 
 endchoice # Which device is eth0
-endif # SAMA5_EMAC0 || SAMA5_EMAC1 || SAMA5_GMAC
+endif # SAMA4_EMAC || SAMA5_EMAC0 || SAMA5_EMAC1 || SAMA5_GMAC
 
 if SAMA5_CAN0 || SAMA5_CAN1
 
diff --git a/nuttx/arch/arm/src/sama5/Make.defs b/nuttx/arch/arm/src/sama5/Make.defs
index 9c2fc7e6c..0183f7565 100644
--- a/nuttx/arch/arm/src/sama5/Make.defs
+++ b/nuttx/arch/arm/src/sama5/Make.defs
@@ -190,7 +190,7 @@ endif
 
 ifeq ($(CONFIG_NET),y)
 CHIP_CSRCS += sam_ethernet.c
-ifeq ($(CONFIG_SAMA5_EMAC0),y)
+ifeq ($(CONFIG_SAMA5_EMAC),y)
 CHIP_CSRCS += sam_emac.c
 endif
 ifeq ($(CONFIG_SAMA5_GMAC),y)
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_emac.h b/nuttx/arch/arm/src/sama5/chip/sam_emac.h
index 13e5c3fb5..f86a8dc97 100644
--- a/nuttx/arch/arm/src/sama5/chip/sam_emac.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_emac.h
@@ -99,99 +99,52 @@
 
 /* EMAC Register Addresses **********************************************************/
 
-#define SAM_EMAC0_NCR             (SAM_EMAC0_VBASE+SAM_EMAC_NCR_OFFSET)
-#define SAM_EMAC0_NCFGR           (SAM_EMAC0_VBASE+SAM_EMAC_NCFGR_OFFSET)
-#define SAM_EMAC0_NSR             (SAM_EMAC0_VBASE+SAM_EMAC_NSR_OFFSET)
-#define SAM_EMAC0_TSR             (SAM_EMAC0_VBASE+SAM_EMAC_TSR_OFFSET)
-#define SAM_EMAC0_RBQP            (SAM_EMAC0_VBASE+SAM_EMAC_RBQP_OFFSET)
-#define SAM_EMAC0_TBQP            (SAM_EMAC0_VBASE+SAM_EMAC_TBQP_OFFSET)
-#define SAM_EMAC0_RSR             (SAM_EMAC0_VBASE+SAM_EMAC_RSR_OFFSET)
-#define SAM_EMAC0_ISR             (SAM_EMAC0_VBASE+SAM_EMAC_ISR_OFFSET)
-#define SAM_EMAC0_IER             (SAM_EMAC0_VBASE+SAM_EMAC_IER_OFFSET)
-#define SAM_EMAC0_IDR             (SAM_EMAC0_VBASE+SAM_EMAC_IDR_OFFSET)
-#define SAM_EMAC0_IMR             (SAM_EMAC0_VBASE+SAM_EMAC_IMR_OFFSET)
-#define SAM_EMAC0_MAN             (SAM_EMAC0_VBASE+SAM_EMAC_MAN_OFFSET)
-#define SAM_EMAC0_PTR             (SAM_EMAC0_VBASE+SAM_EMAC_PTR_OFFSET)
-#define SAM_EMAC0_PFR             (SAM_EMAC0_VBASE+SAM_EMAC_PFR_OFFSET)
-#define SAM_EMAC0_FTO             (SAM_EMAC0_VBASE+SAM_EMAC_FTO_OFFSET)
-#define SAM_EMAC0_SCF             (SAM_EMAC0_VBASE+SAM_EMAC_SCF_OFFSET)
-#define SAM_EMAC0_MCF             (SAM_EMAC0_VBASE+SAM_EMAC_MCF_OFFSET)
-#define SAM_EMAC0_FRO             (SAM_EMAC0_VBASE+SAM_EMAC_FRO_OFFSET)
-#define SAM_EMAC0_FCSE            (SAM_EMAC0_VBASE+SAM_EMAC_FCSE_OFFSET)
-#define SAM_EMAC0_ALE             (SAM_EMAC0_VBASE+SAM_EMAC_ALE_OFFSET)
-#define SAM_EMAC0_DTF             (SAM_EMAC0_VBASE+SAM_EMAC_DTF_OFFSET)
-#define SAM_EMAC0_LCOL            (SAM_EMAC0_VBASE+SAM_EMAC_LCOL_OFFSET)
-#define SAM_EMAC0_ECOL            (SAM_EMAC0_VBASE+SAM_EMAC_ECOL_OFFSET)
-#define SAM_EMAC0_TUND            (SAM_EMAC0_VBASE+SAM_EMAC_TUND_OFFSET)
-#define SAM_EMAC0_CSE             (SAM_EMAC0_VBASE+SAM_EMAC_CSE_OFFSET)
-#define SAM_EMAC0_RRE             (SAM_EMAC0_VBASE+SAM_EMAC_RRE_OFFSET)
-#define SAM_EMAC0_ROV             (SAM_EMAC0_VBASE+SAM_EMAC_ROV_OFFSET)
-#define SAM_EMAC0_RSE             (SAM_EMAC0_VBASE+SAM_EMAC_RSE_OFFSET)
-#define SAM_EMAC0_ELE             (SAM_EMAC0_VBASE+SAM_EMAC_ELE_OFFSET)
-#define SAM_EMAC0_RJA             (SAM_EMAC0_VBASE+SAM_EMAC_RJA_OFFSET)
-#define SAM_EMAC0_USF             (SAM_EMAC0_VBASE+SAM_EMAC_USF_OFFSET)
-#define SAM_EMAC0_STE             (SAM_EMAC0_VBASE+SAM_EMAC_STE_OFFSET)
-#define SAM_EMAC0_RLE             (SAM_EMAC0_VBASE+SAM_EMAC_RLE_OFFSET)
-#define SAM_EMAC0_HRB             (SAM_EMAC0_VBASE+SAM_EMAC_HRB_OFFSET)
-#define SAM_EMAC0_HRT             (SAM_EMAC0_VBASE+SAM_EMAC_HRT_OFFSET)
-#define SAM_EMAC0_SA1B            (SAM_EMAC0_VBASE+SAM_EMAC_SA1B_OFFSET)
-#define SAM_EMAC0_SA1T            (SAM_EMAC0_VBASE+SAM_EMAC_SA1T_OFFSET)
-#define SAM_EMAC0_SA2B            (SAM_EMAC0_VBASE+SAM_EMAC_SA2B_OFFSET)
-#define SAM_EMAC0_SA2T            (SAM_EMAC0_VBASE+SAM_EMAC_SA2T_OFFSET)
-#define SAM_EMAC0_SA3B            (SAM_EMAC0_VBASE+SAM_EMAC_SA3B_OFFSET)
-#define SAM_EMAC0_SA3T            (SAM_EMAC0_VBASE+SAM_EMAC_SA3T_OFFSET)
-#define SAM_EMAC0_SA4B            (SAM_EMAC0_VBASE+SAM_EMAC_SA4B_OFFSET)
-#define SAM_EMAC0_SA4T            (SAM_EMAC0_VBASE+SAM_EMAC_SA4T_OFFSET)
-#define SAM_EMAC0_TID             (SAM_EMAC0_VBASE+SAM_EMAC_TID_OFFSET)
-#define SAM_EMAC0_USRIO           (SAM_EMAC0_VBASE+SAM_EMAC_USRIO_OFFSET)
-#define SAM_EMAC0_WOL             (SAM_EMAC0_VBASE+SAM_EMAC_WOL_OFFSET)
-
-#define SAM_EMAC1_NCR             (SAM_EMAC1_VBASE+SAM_EMAC_NCR_OFFSET)
-#define SAM_EMAC1_NCFGR           (SAM_EMAC1_VBASE+SAM_EMAC_NCFGR_OFFSET)
-#define SAM_EMAC1_NSR             (SAM_EMAC1_VBASE+SAM_EMAC_NSR_OFFSET)
-#define SAM_EMAC1_TSR             (SAM_EMAC1_VBASE+SAM_EMAC_TSR_OFFSET)
-#define SAM_EMAC1_RBQP            (SAM_EMAC1_VBASE+SAM_EMAC_RBQP_OFFSET)
-#define SAM_EMAC1_TBQP            (SAM_EMAC1_VBASE+SAM_EMAC_TBQP_OFFSET)
-#define SAM_EMAC1_RSR             (SAM_EMAC1_VBASE+SAM_EMAC_RSR_OFFSET)
-#define SAM_EMAC1_ISR             (SAM_EMAC1_VBASE+SAM_EMAC_ISR_OFFSET)
-#define SAM_EMAC1_IER             (SAM_EMAC1_VBASE+SAM_EMAC_IER_OFFSET)
-#define SAM_EMAC1_IDR             (SAM_EMAC1_VBASE+SAM_EMAC_IDR_OFFSET)
-#define SAM_EMAC1_IMR             (SAM_EMAC1_VBASE+SAM_EMAC_IMR_OFFSET)
-#define SAM_EMAC1_MAN             (SAM_EMAC1_VBASE+SAM_EMAC_MAN_OFFSET)
-#define SAM_EMAC1_PTR             (SAM_EMAC1_VBASE+SAM_EMAC_PTR_OFFSET)
-#define SAM_EMAC1_PFR             (SAM_EMAC1_VBASE+SAM_EMAC_PFR_OFFSET)
-#define SAM_EMAC1_FTO             (SAM_EMAC1_VBASE+SAM_EMAC_FTO_OFFSET)
-#define SAM_EMAC1_SCF             (SAM_EMAC1_VBASE+SAM_EMAC_SCF_OFFSET)
-#define SAM_EMAC1_MCF             (SAM_EMAC1_VBASE+SAM_EMAC_MCF_OFFSET)
-#define SAM_EMAC1_FRO             (SAM_EMAC1_VBASE+SAM_EMAC_FRO_OFFSET)
-#define SAM_EMAC1_FCSE            (SAM_EMAC1_VBASE+SAM_EMAC_FCSE_OFFSET)
-#define SAM_EMAC1_ALE             (SAM_EMAC1_VBASE+SAM_EMAC_ALE_OFFSET)
-#define SAM_EMAC1_DTF             (SAM_EMAC1_VBASE+SAM_EMAC_DTF_OFFSET)
-#define SAM_EMAC1_LCOL            (SAM_EMAC1_VBASE+SAM_EMAC_LCOL_OFFSET)
-#define SAM_EMAC1_ECOL            (SAM_EMAC1_VBASE+SAM_EMAC_ECOL_OFFSET)
-#define SAM_EMAC1_TUND            (SAM_EMAC1_VBASE+SAM_EMAC_TUND_OFFSET)
-#define SAM_EMAC1_CSE             (SAM_EMAC1_VBASE+SAM_EMAC_CSE_OFFSET)
-#define SAM_EMAC1_RRE             (SAM_EMAC1_VBASE+SAM_EMAC_RRE_OFFSET)
-#define SAM_EMAC1_ROV             (SAM_EMAC1_VBASE+SAM_EMAC_ROV_OFFSET)
-#define SAM_EMAC1_RSE             (SAM_EMAC1_VBASE+SAM_EMAC_RSE_OFFSET)
-#define SAM_EMAC1_ELE             (SAM_EMAC1_VBASE+SAM_EMAC_ELE_OFFSET)
-#define SAM_EMAC1_RJA             (SAM_EMAC1_VBASE+SAM_EMAC_RJA_OFFSET)
-#define SAM_EMAC1_USF             (SAM_EMAC1_VBASE+SAM_EMAC_USF_OFFSET)
-#define SAM_EMAC1_STE             (SAM_EMAC1_VBASE+SAM_EMAC_STE_OFFSET)
-#define SAM_EMAC1_RLE             (SAM_EMAC1_VBASE+SAM_EMAC_RLE_OFFSET)
-#define SAM_EMAC1_HRB             (SAM_EMAC1_VBASE+SAM_EMAC_HRB_OFFSET)
-#define SAM_EMAC1_HRT             (SAM_EMAC1_VBASE+SAM_EMAC_HRT_OFFSET)
-#define SAM_EMAC1_SA1B            (SAM_EMAC1_VBASE+SAM_EMAC_SA1B_OFFSET)
-#define SAM_EMAC1_SA1T            (SAM_EMAC1_VBASE+SAM_EMAC_SA1T_OFFSET)
-#define SAM_EMAC1_SA2B            (SAM_EMAC1_VBASE+SAM_EMAC_SA2B_OFFSET)
-#define SAM_EMAC1_SA2T            (SAM_EMAC1_VBASE+SAM_EMAC_SA2T_OFFSET)
-#define SAM_EMAC1_SA3B            (SAM_EMAC1_VBASE+SAM_EMAC_SA3B_OFFSET)
-#define SAM_EMAC1_SA3T            (SAM_EMAC1_VBASE+SAM_EMAC_SA3T_OFFSET)
-#define SAM_EMAC1_SA4B            (SAM_EMAC1_VBASE+SAM_EMAC_SA4B_OFFSET)
-#define SAM_EMAC1_SA4T            (SAM_EMAC1_VBASE+SAM_EMAC_SA4T_OFFSET)
-#define SAM_EMAC1_TID             (SAM_EMAC1_VBASE+SAM_EMAC_TID_OFFSET)
-#define SAM_EMAC1_USRIO           (SAM_EMAC1_VBASE+SAM_EMAC_USRIO_OFFSET)
-#define SAM_EMAC1_WOL             (SAM_EMAC1_VBASE+SAM_EMAC_WOL_OFFSET)
+#define SAM_EMAC_NCR              (SAM_EMAC_VBASE+SAM_EMAC_NCR_OFFSET)
+#define SAM_EMAC_NCFGR            (SAM_EMAC_VBASE+SAM_EMAC_NCFGR_OFFSET)
+#define SAM_EMAC_NSR              (SAM_EMAC_VBASE+SAM_EMAC_NSR_OFFSET)
+#define SAM_EMAC_TSR              (SAM_EMAC_VBASE+SAM_EMAC_TSR_OFFSET)
+#define SAM_EMAC_RBQP             (SAM_EMAC_VBASE+SAM_EMAC_RBQP_OFFSET)
+#define SAM_EMAC_TBQP             (SAM_EMAC_VBASE+SAM_EMAC_TBQP_OFFSET)
+#define SAM_EMAC_RSR              (SAM_EMAC_VBASE+SAM_EMAC_RSR_OFFSET)
+#define SAM_EMAC_ISR              (SAM_EMAC_VBASE+SAM_EMAC_ISR_OFFSET)
+#define SAM_EMAC_IER              (SAM_EMAC_VBASE+SAM_EMAC_IER_OFFSET)
+#define SAM_EMAC_IDR              (SAM_EMAC_VBASE+SAM_EMAC_IDR_OFFSET)
+#define SAM_EMAC_IMR              (SAM_EMAC_VBASE+SAM_EMAC_IMR_OFFSET)
+#define SAM_EMAC_MAN              (SAM_EMAC_VBASE+SAM_EMAC_MAN_OFFSET)
+#define SAM_EMAC_PTR              (SAM_EMAC_VBASE+SAM_EMAC_PTR_OFFSET)
+#define SAM_EMAC_PFR              (SAM_EMAC_VBASE+SAM_EMAC_PFR_OFFSET)
+#define SAM_EMAC_FTO              (SAM_EMAC_VBASE+SAM_EMAC_FTO_OFFSET)
+#define SAM_EMAC_SCF              (SAM_EMAC_VBASE+SAM_EMAC_SCF_OFFSET)
+#define SAM_EMAC_MCF              (SAM_EMAC_VBASE+SAM_EMAC_MCF_OFFSET)
+#define SAM_EMAC_FRO              (SAM_EMAC_VBASE+SAM_EMAC_FRO_OFFSET)
+#define SAM_EMAC_FCSE             (SAM_EMAC_VBASE+SAM_EMAC_FCSE_OFFSET)
+#define SAM_EMAC_ALE              (SAM_EMAC_VBASE+SAM_EMAC_ALE_OFFSET)
+#define SAM_EMAC_DTF              (SAM_EMAC_VBASE+SAM_EMAC_DTF_OFFSET)
+#define SAM_EMAC_LCOL             (SAM_EMAC_VBASE+SAM_EMAC_LCOL_OFFSET)
+#define SAM_EMAC_ECOL             (SAM_EMAC_VBASE+SAM_EMAC_ECOL_OFFSET)
+#define SAM_EMAC_TUND             (SAM_EMAC_VBASE+SAM_EMAC_TUND_OFFSET)
+#define SAM_EMAC_CSE              (SAM_EMAC_VBASE+SAM_EMAC_CSE_OFFSET)
+#define SAM_EMAC_RRE              (SAM_EMAC_VBASE+SAM_EMAC_RRE_OFFSET)
+#define SAM_EMAC_ROV              (SAM_EMAC_VBASE+SAM_EMAC_ROV_OFFSET)
+#define SAM_EMAC_RSE              (SAM_EMAC_VBASE+SAM_EMAC_RSE_OFFSET)
+#define SAM_EMAC_ELE              (SAM_EMAC_VBASE+SAM_EMAC_ELE_OFFSET)
+#define SAM_EMAC_RJA              (SAM_EMAC_VBASE+SAM_EMAC_RJA_OFFSET)
+#define SAM_EMAC_USF              (SAM_EMAC_VBASE+SAM_EMAC_USF_OFFSET)
+#define SAM_EMAC_STE              (SAM_EMAC_VBASE+SAM_EMAC_STE_OFFSET)
+#define SAM_EMAC_RLE              (SAM_EMAC_VBASE+SAM_EMAC_RLE_OFFSET)
+#define SAM_EMAC_HRB              (SAM_EMAC_VBASE+SAM_EMAC_HRB_OFFSET)
+#define SAM_EMAC_HRT              (SAM_EMAC_VBASE+SAM_EMAC_HRT_OFFSET)
+#define SAM_EMAC_SA1B             (SAM_EMAC_VBASE+SAM_EMAC_SA1B_OFFSET)
+#define SAM_EMAC_SA1T             (SAM_EMAC_VBASE+SAM_EMAC_SA1T_OFFSET)
+#define SAM_EMAC_SA2B             (SAM_EMAC_VBASE+SAM_EMAC_SA2B_OFFSET)
+#define SAM_EMAC_SA2T             (SAM_EMAC_VBASE+SAM_EMAC_SA2T_OFFSET)
+#define SAM_EMAC_SA3B             (SAM_EMAC_VBASE+SAM_EMAC_SA3B_OFFSET)
+#define SAM_EMAC_SA3T             (SAM_EMAC_VBASE+SAM_EMAC_SA3T_OFFSET)
+#define SAM_EMAC_SA4B             (SAM_EMAC_VBASE+SAM_EMAC_SA4B_OFFSET)
+#define SAM_EMAC_SA4T             (SAM_EMAC_VBASE+SAM_EMAC_SA4T_OFFSET)
+#define SAM_EMAC_TID              (SAM_EMAC_VBASE+SAM_EMAC_TID_OFFSET)
+#define SAM_EMAC_USRIO            (SAM_EMAC_VBASE+SAM_EMAC_USRIO_OFFSET)
+#define SAM_EMAC_WOL              (SAM_EMAC_VBASE+SAM_EMAC_WOL_OFFSET)
 
 /* EMAC Register Bit Definitions ****************************************************/
 
diff --git a/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h b/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
index c3363ebef..310111fd7 100644
--- a/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
+++ b/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
@@ -129,7 +129,7 @@
 #  define SAM_USART2_OFFSET      0x00020000 /* 0x00020000-0x00023fff: USART2 */
 #  define SAM_USART3_OFFSET      0x00024000 /* 0x00024000-0x00027fff: USART3 */
 #  define SAM_UART1_OFFSET       0x00028000 /* 0x00028000-0x0002bfff: UART1 */
-#  define SAM_EMAC0_OFFSET       0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
+#  define SAM_EMAC_OFFSET        0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
 #  define SAM_UDPHS_OFFSET       0x00030000 /* 0x00030000-0x00033fff: UDPHS */
 #  define SAM_SHA_OFFSET         0x00034000 /* 0x00034000-0x00037fff: SHA */
 #  define SAM_AES_OFFSET         0x00038000 /* 0x00038000-0x0003bfff: AES */
@@ -414,7 +414,7 @@
 #define SAM_USART2_VBASE         (SAM_PERIPHB_VSECTION+SAM_USART2_OFFSET)
 #define SAM_USART3_VBASE         (SAM_PERIPHB_VSECTION+SAM_USART3_OFFSET)
 #define SAM_UART1_VBASE          (SAM_PERIPHB_VSECTION+SAM_UART1_OFFSET)
-#define SAM_EMAC0_VBASE          (SAM_PERIPHB_VSECTION+SAM_EMAC0_OFFSET)
+#define SAM_EMAC_VBASE           (SAM_PERIPHB_VSECTION+SAM_EMAC_OFFSET)
 #define SAM_UDPHS_VBASE          (SAM_PERIPHB_VSECTION+SAM_UDPHS_OFFSET)
 #define SAM_SHA_VBASE            (SAM_PERIPHB_VSECTION+SAM_SHA_OFFSET)
 #define SAM_AES_VBASE            (SAM_PERIPHB_VSECTION+SAM_AES_OFFSET)
diff --git a/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h b/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
index 0b9c11ec0..b9544671c 100644
--- a/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
+++ b/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
@@ -133,16 +133,16 @@
 
 /* RMII Ethernet 10/100 - EMAC */
 
-#define PIO_EMAC0_CRSDV   (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN5)  /* Type: GPIO */
-#define PIO_EMAC0_MDC     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN8)  /* Type: GPIO */
-#define PIO_EMAC0_MDIO    (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN9)  /* Type: GPIO */
-#define PIO_EMAC0_REFCK   (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN7)  /* Type: GPIO */
-#define PIO_EMAC0_RX0     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN2)  /* Type: GPIO */
-#define PIO_EMAC0_RX1     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN3)  /* Type: GPIO */
-#define PIO_EMAC0_RXER    (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN6)  /* Type: GPIO */
-#define PIO_EMAC0_TX0     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN0)  /* Type: GPIO */
-#define PIO_EMAC0_TX1     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN1)  /* Type: GPIO */
-#define PIO_EMAC0_TXEN    (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN4)  /* Type: GPIO */
+#define PIO_EMAC_CRSDV    (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN5)  /* Type: GPIO */
+#define PIO_EMAC_MDC      (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN8)  /* Type: GPIO */
+#define PIO_EMAC_MDIO     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN9)  /* Type: GPIO */
+#define PIO_EMAC_REFCK    (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN7)  /* Type: GPIO */
+#define PIO_EMAC_RX0      (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN2)  /* Type: GPIO */
+#define PIO_EMAC_RX1      (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN3)  /* Type: GPIO */
+#define PIO_EMAC_RXER     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN6)  /* Type: GPIO */
+#define PIO_EMAC_TX0      (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN0)  /* Type: GPIO */
+#define PIO_EMAC_TX1      (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN1)  /* Type: GPIO */
+#define PIO_EMAC_TXEN     (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN4)  /* Type: GPIO */
 
 /* GIgabit Ethernet 10/100/1000 - GMAC */
 
diff --git a/nuttx/arch/arm/src/sama5/sam_emac.c b/nuttx/arch/arm/src/sama5/sam_emac.c
index c6a84e639..b62f39b63 100644
--- a/nuttx/arch/arm/src/sama5/sam_emac.c
+++ b/nuttx/arch/arm/src/sama5/sam_emac.c
@@ -78,7 +78,7 @@
 
 #include <arch/board/board.h>
 
-#if defined(CONFIG_NET) && defined(CONFIG_SAMA5_EMAC0)
+#if defined(CONFIG_NET) && defined(CONFIG_SAMA5_EMAC)
 
 /****************************************************************************
  * Definitions
@@ -87,62 +87,62 @@
 
 /* Number of buffer for RX */
 
-#ifndef CONFIG_SAMA5_EMAC0_NRXBUFFERS
-#  define CONFIG_SAMA5_EMAC0_NRXBUFFERS  16
+#ifndef CONFIG_SAMA5_EMAC_NRXBUFFERS
+#  define CONFIG_SAMA5_EMAC_NRXBUFFERS  16
 #endif
 
 /* Number of buffer for TX */
 
-#ifndef CONFIG_SAMA5_EMAC0_NTXBUFFERS
-#  define CONFIG_SAMA5_EMAC0_NTXBUFFERS  8
+#ifndef CONFIG_SAMA5_EMAC_NTXBUFFERS
+#  define CONFIG_SAMA5_EMAC_NTXBUFFERS  8
 #endif
 
-#undef CONFIG_SAMA5_EMAC0_NBC
+#undef CONFIG_SAMA5_EMAC_NBC
 
-#ifndef CONFIG_SAMA5_EMAC0_PHYADDR
-#  error "CONFIG_SAMA5_EMAC0_PHYADDR must be defined in the NuttX configuration"
+#ifndef CONFIG_SAMA5_EMAC_PHYADDR
+#  error "CONFIG_SAMA5_EMAC_PHYADDR must be defined in the NuttX configuration"
 #endif
 
-#if !defined(CONFIG_SAMA5_EMAC0_MII) && !defined(CONFIG_SAMA5_EMAC0_RMII)
-#  warning "Neither CONFIG_SAMA5_EMAC0_MII nor CONFIG_SAMA5_EMAC0_RMII defined"
+#if !defined(CONFIG_SAMA5_EMAC_MII) && !defined(CONFIG_SAMA5_EMAC_RMII)
+#  warning "Neither CONFIG_SAMA5_EMAC_MII nor CONFIG_SAMA5_EMAC_RMII defined"
 #endif
 
-#if defined(CONFIG_SAMA5_EMAC0_MII) && defined(CONFIG_SAMA5_EMAC0_RMII)
-#  error "Both CONFIG_SAMA5_EMAC0_MII and CONFIG_SAMA5_EMAC0_RMII defined"
+#if defined(CONFIG_SAMA5_EMAC_MII) && defined(CONFIG_SAMA5_EMAC_RMII)
+#  error "Both CONFIG_SAMA5_EMAC_MII and CONFIG_SAMA5_EMAC_RMII defined"
 #endif
 
-#ifdef CONFIG_SAMA5_EMAC0_AUTONEG
-#  ifndef CONFIG_SAMA5_EMAC0_PHYSR
-#    error "CONFIG_SAMA5_EMAC0_PHYSR must be defined in the NuttX configuration"
+#ifdef CONFIG_SAMA5_EMAC_AUTONEG
+#  ifndef CONFIG_SAMA5_EMAC_PHYSR
+#    error "CONFIG_SAMA5_EMAC_PHYSR must be defined in the NuttX configuration"
 #  endif
-#  ifdef CONFIG_SAMA5_EMAC0_PHYSR_ALTCONFIG
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_ALTMODE
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_ALTMODE must be defined in the NuttX configuration"
+#  ifdef CONFIG_SAMA5_EMAC_PHYSR_ALTCONFIG
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_ALTMODE
+#      error "CONFIG_SAMA5_EMAC_PHYSR_ALTMODE must be defined in the NuttX configuration"
 #    endif
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_10HD
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_10HD must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_10HD
+#      error "CONFIG_SAMA5_EMAC_PHYSR_10HD must be defined in the NuttX configuration"
 #    endif
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_100HD
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_100HD must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_100HD
+#      error "CONFIG_SAMA5_EMAC_PHYSR_100HD must be defined in the NuttX configuration"
 #    endif
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_10FD
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_10FD must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_10FD
+#      error "CONFIG_SAMA5_EMAC_PHYSR_10FD must be defined in the NuttX configuration"
 #    endif
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_100FD
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_100FD must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_100FD
+#      error "CONFIG_SAMA5_EMAC_PHYSR_100FD must be defined in the NuttX configuration"
 #    endif
 #  else
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_SPEED
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_SPEED must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_SPEED
+#      error "CONFIG_SAMA5_EMAC_PHYSR_SPEED must be defined in the NuttX configuration"
 #    endif
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_100MBPS
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_100MBPS must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_100MBPS
+#      error "CONFIG_SAMA5_EMAC_PHYSR_100MBPS must be defined in the NuttX configuration"
 #    endif
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_MODE
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_MODE must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_MODE
+#      error "CONFIG_SAMA5_EMAC_PHYSR_MODE must be defined in the NuttX configuration"
 #    endif
-#    ifndef CONFIG_SAMA5_EMAC0_PHYSR_FULLDUPLEX
-#      error "CONFIG_SAMA5_EMAC0_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
+#    ifndef CONFIG_SAMA5_EMAC_PHYSR_FULLDUPLEX
+#      error "CONFIG_SAMA5_EMAC_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
 #    endif
 #  endif
 #endif
@@ -162,15 +162,15 @@
 #  error EMAC PHY unrecognized
 #endif
 
-#ifdef CONFIG_SAMA5_EMAC0_PHYSR_ALTCONFIG
+#ifdef CONFIG_SAMA5_EMAC_PHYSR_ALTCONFIG
 
-#  define PHYSR_MODE(sr)     ((sr) & CONFIG_SAMA5_EMAC0_PHYSR_ALTMODE)
+#  define PHYSR_MODE(sr)     ((sr) & CONFIG_SAMA5_EMAC_PHYSR_ALTMODE)
 #  define PHYSR_ISMODE(sr,m) (PHYSR_MODE(sr) == (m))
 
-#  define PHYSR_IS10HDX(sr)  PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC0_PHYSR_10HD)
-#  define PHYSR_IS100HDX(sr) PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC0_PHYSR_100HD)
-#  define PHYSR_IS10FDX(sr)  PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC0_PHYSR_10FD)
-#  define PHYSR_IS100FDX(sr) PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC0_PHYSR_100FD)
+#  define PHYSR_IS10HDX(sr)  PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC_PHYSR_10HD)
+#  define PHYSR_IS100HDX(sr) PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC_PHYSR_100HD)
+#  define PHYSR_IS10FDX(sr)  PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC_PHYSR_10FD)
+#  define PHYSR_IS100FDX(sr) PHYSR_ISMODE(sr,CONFIG_SAMA5_EMAC_PHYSR_100FD)
 
 #else
 
@@ -205,14 +205,14 @@
 
 /* We need at least one more free buffer than transmit buffers */
 
-#define SAM_EMAC_NFREEBUFFERS (CONFIG_SAMA5_EMAC0_NTXBUFFERS+1)
+#define SAM_EMAC_NFREEBUFFERS (CONFIG_SAMA5_EMAC_NTXBUFFERS+1)
 
 /* Extremely detailed register debug that you would normally never want
  * enabled.
  */
 
 #ifndef CONFIG_DEBUG
-#  undef CONFIG_SAMA5_EMAC0_REGDEBUG
+#  undef CONFIG_SAMA5_EMAC_REGDEBUG
 #endif
 
 #ifdef CONFIG_NET_DUMPPACKET
@@ -274,7 +274,7 @@ struct sam_emac_s
 
   /* Debug stuff */
 
-#ifdef CONFIG_SAMA5_EMAC0_REGDEBUG
+#ifdef CONFIG_SAMA5_EMAC_REGDEBUG
    bool               wrlast;     /* Last was a write */
    uintptr_t          addrlast;   /* Last address */
    uint32_t           vallast;    /* Last value */
@@ -290,16 +290,16 @@ struct sam_emac_s
 
 static struct sam_emac_s g_emac;
 
-#ifdef CONFIG_SAMA5_EMAC0_PREALLOCATE
+#ifdef CONFIG_SAMA5_EMAC_PREALLOCATE
 /* Preallocated data */
 /* TX descriptors list */
 
-static struct emac_txdesc_s g_txdesc[CONFIG_SAMA5_EMAC0_NTXBUFFERS]
+static struct emac_txdesc_s g_txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS]
               __attribute__((aligned(8)));
 
 /* RX descriptors list */
 
-static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC0_NRXBUFFERS]
+static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC_NRXBUFFERS]
               __attribute__((aligned(8)));
 
 /* Transmit Buffers
@@ -309,12 +309,12 @@ static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC0_NRXBUFFERS]
  * shall be set to 0
  */
 
-static uint8_t g_txbuffer[CONFIG_SAMA5_EMAC0_NTXBUFFERS * EMAC_TX_UNITSIZE];
+static uint8_t g_txbuffer[CONFIG_SAMA5_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE];
                __attribute__((aligned(8)))
 
 /* Receive Buffers */
 
-static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC0_NRXBUFFERS * EMAC_RX_UNITSIZE]
+static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
                __attribute__((aligned(8)));
 
 #endif
@@ -324,7 +324,7 @@ static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC0_NRXBUFFERS * EMAC_RX_UNITSIZE]
  ****************************************************************************/
 /* Register operations ******************************************************/
 
-#if defined(CONFIG_SAMA5_EMAC0_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_SAMA5_EMAC_REGDEBUG) && defined(CONFIG_DEBUG)
 static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
                          uint32_t regval, uintptr_t address);
 static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr);
@@ -415,7 +415,7 @@ static int  sam_emac_configure(struct sam_emac_s *priv);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SAMA5_EMAC0_REGDEBUG
+#ifdef CONFIG_SAMA5_EMAC_REGDEBUG
 static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
                          uintptr_t address)
 {
@@ -461,7 +461,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SAMA5_EMAC0_REGDEBUG
+#ifdef CONFIG_SAMA5_EMAC_REGDEBUG
 static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
 {
   uint32_t regval = getreg32(address);
@@ -483,7 +483,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SAMA5_EMAC0_REGDEBUG
+#ifdef CONFIG_SAMA5_EMAC_REGDEBUG
 static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
                        uint32_t regval)
 {
@@ -515,7 +515,7 @@ static uint16_t sam_txinuse(struct sam_emac_s *priv)
   uint32_t txhead32 = (uint32_t)priv->txhead;
   if ((uint32_t)priv->txtail > txhead32)
     {
-      return txhead32 += CONFIG_SAMA5_EMAC0_NTXBUFFERS;
+      return txhead32 += CONFIG_SAMA5_EMAC_NTXBUFFERS;
     }
 
   return (uint16_t)(txhead32 - (uint32_t)priv->txtail);
@@ -542,7 +542,7 @@ static uint16_t sam_txfree(struct sam_emac_s *priv)
    * the configured size minus 1.
    */
 
-  return (CONFIG_SAMA5_EMAC0_NTXBUFFERS-1) - sam_txinuse(priv);
+  return (CONFIG_SAMA5_EMAC_NTXBUFFERS-1) - sam_txinuse(priv);
 }
 
 /****************************************************************************
@@ -565,7 +565,7 @@ static uint16_t sam_txfree(struct sam_emac_s *priv)
 
 static int sam_buffer_initialize(struct sam_emac_s *priv)
 {
-#ifdef CONFIG_SAMA5_EMAC0_PREALLOCATE
+#ifdef CONFIG_SAMA5_EMAC_PREALLOCATE
   /* Use pre-allocated buffers */
 
   priv->txdesc   = g_txdesc;
@@ -578,7 +578,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
 
   /* Allocate buffers */
 
-  allocsize = CONFIG_SAMA5_EMAC0_NTXBUFFERS * sizeof(struct emac_txdesc_s);
+  allocsize = CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s);
   priv->txdesc = (struct emac_txdesc_s *)kmemalign(8, allocsize);
   if (!priv->txdesc)
     {
@@ -588,7 +588,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
 
   memset(priv->txdesc, 0, allocsize);
 
-  allocsize = CONFIG_SAMA5_EMAC0_NRXBUFFERS * sizeof(struct emac_rxdesc_s);
+  allocsize = CONFIG_SAMA5_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s);
   priv->rxdesc = (struct emac_rxdesc_s *)kmemalign(8, allocsize);
   if (!priv->rxdesc)
     {
@@ -599,7 +599,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
 
   memset(priv->rxdesc, 0, allocsize);
 
-  allocsize = CONFIG_SAMA5_EMAC0_NTXBUFFERS * EMAC_TX_UNITSIZE;
+  allocsize = CONFIG_SAMA5_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE;
   priv->txbuffer = (uint8_t *)kmemalign(8, allocsize);
   if (!priv->txbuffer)
     {
@@ -608,7 +608,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
       return -ENOMEM;
     }
 
-  allocsize = CONFIG_SAMA5_EMAC0_NRXBUFFERS * EMAC_RX_UNITSIZE;
+  allocsize = CONFIG_SAMA5_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE;
   priv->rxbuffer = (uint8_t *)kmemalign(8, allocsize);
   if (!priv->rxbuffer)
     {
@@ -643,7 +643,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
 
 static void sam_buffer_free(struct sam_emac_s *priv)
 {
-#ifndef CONFIG_SAMA5_EMAC0_PREALLOCATE
+#ifndef CONFIG_SAMA5_EMAC_PREALLOCATE
   /* Free allocated buffers */
 
   if (priv->txdesc)
@@ -737,7 +737,7 @@ static int sam_transmit(struct sam_emac_s *priv)
   /* Update TX descriptor status. */
 
   status = dev->d_len | EMACTXD_STA_LAST;
-  if (priv->txhead == CONFIG_SAMA5_EMAC0_NTXBUFFERS-1)
+  if (priv->txhead == CONFIG_SAMA5_EMAC_NTXBUFFERS-1)
     {
       status |= EMACTXD_STA_WRAP;
     }
@@ -750,16 +750,16 @@ static int sam_transmit(struct sam_emac_s *priv)
 
   /* Increment the head index */
 
-  if (++priv->txhead >= CONFIG_SAMA5_EMAC0_NTXBUFFERS)
+  if (++priv->txhead >= CONFIG_SAMA5_EMAC_NTXBUFFERS)
     {
       priv->txhead = 0;
     }
 
   /* Now start transmission (if it is not already done) */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= EMAC_NCR_TSTART;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Setup the TX timeout watchdog (perhaps restarting the timer) */
 
@@ -782,7 +782,7 @@ static int sam_transmit(struct sam_emac_s *priv)
   if (sam_txfree(priv) < 1)
     {
       nllvdbg("Disabling RX interrupts\n");
-      sam_putreg(priv, SAM_EMAC0_IDR, EMAC_INT_RCOMP);
+      sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
     }
 
   return OK;
@@ -959,7 +959,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
 
               /* Increment the RX index */
 
-              if (++priv->rxndx >= CONFIG_SAMA5_EMAC0_NRXBUFFERS)
+              if (++priv->rxndx >= CONFIG_SAMA5_EMAC_NRXBUFFERS)
                 {
                   priv->rxndx = 0;
                 }
@@ -977,7 +977,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
 
       /* Increment the working index */
 
-      if (++rxndx >= CONFIG_SAMA5_EMAC0_NRXBUFFERS)
+      if (++rxndx >= CONFIG_SAMA5_EMAC_NRXBUFFERS)
         {
           rxndx = 0;
         }
@@ -1004,7 +1004,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
 
                   /* Increment the RX index */
 
-                  if (++priv->rxndx >= CONFIG_SAMA5_EMAC0_NRXBUFFERS)
+                  if (++priv->rxndx >= CONFIG_SAMA5_EMAC_NRXBUFFERS)
                     {
                       priv->rxndx = 0;
                     }
@@ -1064,7 +1064,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
 
                   /* Increment the RX index */
 
-                  if (++priv->rxndx >= CONFIG_SAMA5_EMAC0_NRXBUFFERS)
+                  if (++priv->rxndx >= CONFIG_SAMA5_EMAC_NRXBUFFERS)
                     {
                       priv->rxndx = 0;
                     }
@@ -1257,7 +1257,7 @@ static void sam_txdone(struct sam_emac_s *priv)
 #if 0 /* The issue does not exist in the current configuration, but may return */
 #warning REVISIT
           if (priv->txtail == 0 &&
-              sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC0_TBQP))
+              sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQP))
             {
               txdesc->status = (uint32_t)EMACTXD_STA_USED;
               cp15_clean_dcache((uintptr_t)txdesc,
@@ -1276,7 +1276,7 @@ static void sam_txdone(struct sam_emac_s *priv)
 
       /* Increment the tail index */
 
-      if (++priv->txtail >= CONFIG_SAMA5_EMAC0_NTXBUFFERS)
+      if (++priv->txtail >= CONFIG_SAMA5_EMAC_NTXBUFFERS)
         {
           /* Wrap to the beginning of the TX descriptor list */
 
@@ -1288,7 +1288,7 @@ static void sam_txdone(struct sam_emac_s *priv)
        * TX desciptors (see commits in sam_transmit()).
        */
 
-      sam_putreg(priv, SAM_EMAC0_IER, EMAC_INT_RCOMP);
+      sam_putreg(priv, SAM_EMAC_IER, EMAC_INT_RCOMP);
     }
 
   /* Then poll uIP for new XMIT data */
@@ -1324,10 +1324,10 @@ static int sam_emac_interrupt(int irq, void *context)
   uint32_t pending;
   uint32_t clrbits;
 
-  isr = sam_getreg(priv, SAM_EMAC0_ISR);
-  rsr = sam_getreg(priv, SAM_EMAC0_RSR);
-  tsr = sam_getreg(priv, SAM_EMAC0_TSR);
-  imr = sam_getreg(priv, SAM_EMAC0_IMR);
+  isr = sam_getreg(priv, SAM_EMAC_ISR);
+  rsr = sam_getreg(priv, SAM_EMAC_RSR);
+  tsr = sam_getreg(priv, SAM_EMAC_TSR);
+  imr = sam_getreg(priv, SAM_EMAC_IMR);
 
   pending = isr & ~(imr | EMAC_INT_UNUSED);
   nllvdbg("isr: %08x pending: %08x\n", isr, pending);
@@ -1358,9 +1358,9 @@ static int sam_emac_interrupt(int irq, void *context)
 
           nlldbg("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
 
-          regval = sam_getreg(priv, SAM_EMAC0_NCR);
+          regval = sam_getreg(priv, SAM_EMAC_NCR);
           regval |= EMAC_NCR_TE;
-          sam_putreg(priv, SAM_EMAC0_NCR, regval);
+          sam_putreg(priv, SAM_EMAC_NCR, regval);
         }
 
       /* Check Collision Occurred (COL) */
@@ -1396,7 +1396,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
       /* Clear status */
 
-      sam_putreg(priv, SAM_EMAC0_TSR, clrbits);
+      sam_putreg(priv, SAM_EMAC_TSR, clrbits);
 
       /* And handle the TX done event */
 
@@ -1450,7 +1450,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
       /* Clear status */
 
-      sam_putreg(priv, SAM_EMAC0_RSR, clrbits);
+      sam_putreg(priv, SAM_EMAC_RSR, clrbits);
 
       /* Handle the received packet */
 
@@ -1625,7 +1625,7 @@ static int sam_ifup(struct uip_driver_s *dev)
   /* Enable the EMAC interrupt */
 
   priv->ifup = true;
-  up_enable_irq(SAM_IRQ_EMAC0);
+  up_enable_irq(SAM_IRQ_EMAC);
   return OK;
 }
 
@@ -1655,7 +1655,7 @@ static int sam_ifdown(struct uip_driver_s *dev)
   /* Disable the EMAC interrupt */
 
   flags = irqsave();
-  up_disable_irq(SAM_IRQ_EMAC0);
+  up_disable_irq(SAM_IRQ_EMAC);
 
   /* Cancel the TX poll timer and TX timeout timers */
 
@@ -1810,13 +1810,13 @@ static void sam_phydump(struct sam_emac_s *priv)
 
   /* Enable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
-#ifdef CONFIG_SAMA5_EMAC0_RMII
+#ifdef CONFIG_SAMA5_EMAC_RMII
   nllvdbg("RMII Registers (Address %02x)\n", priv->phyaddr);
-#else /* defined(CONFIG_SAMA5_EMAC0_MII) */
+#else /* defined(CONFIG_SAMA5_EMAC_MII) */
   nllvdbg("MII Registers (Address %02x)\n", priv->phyaddr);
 #endif
 
@@ -1828,14 +1828,14 @@ static void sam_phydump(struct sam_emac_s *priv)
   nllvdbg("  ADVERTISE: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
   nllvdbg("  LPR:       %04x\n", phyval);
-  sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC0_PHYSR, &phyval);
+  sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
   nllvdbg("  PHYSR:     %04x\n", phyval);
 
   /* Disable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval &= ~EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 }
 #endif
 
@@ -1863,7 +1863,7 @@ static int sam_phywait(struct sam_emac_s *priv)
     {
       /* Is the PHY IDLE */
 
-      if ((sam_getreg(priv, SAM_EMAC0_NSR) & EMAC_NSR_IDLE) != 0)
+      if ((sam_getreg(priv, SAM_EMAC_NSR) & EMAC_NSR_IDLE) != 0)
         {
           return OK;
         }
@@ -1899,9 +1899,9 @@ static int sam_phyreset(struct sam_emac_s *priv)
 
   /* Enable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Reset the PHY */
 
@@ -1932,9 +1932,9 @@ static int sam_phyreset(struct sam_emac_s *priv)
 
   /* Disable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval &= ~EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
   return ret;
 }
 
@@ -1966,9 +1966,9 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
 
   /* Enable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   candidate = *phyaddr;
 
@@ -2009,15 +2009,15 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
     {
       nllvdbg("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
       *phyaddr = candidate;
-      sam_phyread(priv, candidate, CONFIG_SAMA5_EMAC0_PHYSR, &phyval);
+      sam_phyread(priv, candidate, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
       nllvdbg("  PHYSR:  %04x PHY addr: %d\n", phyval, candidate);
     }
 
   /* Disable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval &= ~EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
   return ret;
 }
 
@@ -2059,7 +2059,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
 
   regval = EMAC_MAN_DATA(0) | EMAC_MAN_CODE | EMAC_MAN_REGA(regaddr) |
            EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_READ | EMAC_MAN_SOF;
-  sam_putreg(priv, SAM_EMAC0_MAN, regval);
+  sam_putreg(priv, SAM_EMAC_MAN, regval);
 
   /* Wait until the PHY is again idle */
 
@@ -2072,7 +2072,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
 
   /* Return data */
 
-  *phyval = (uint16_t)(sam_getreg(priv, SAM_EMAC0_MAN) & EMAC_MAN_DATA_MASK);
+  *phyval = (uint16_t)(sam_getreg(priv, SAM_EMAC_MAN) & EMAC_MAN_DATA_MASK);
   return OK;
 }
 
@@ -2114,7 +2114,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
 
   regval = EMAC_MAN_DATA(phyval) | EMAC_MAN_CODE | EMAC_MAN_REGA(regaddr) |
            EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_WRITE| EMAC_MAN_SOF;
-  sam_putreg(priv, SAM_EMAC0_MAN, regval);
+  sam_putreg(priv, SAM_EMAC_MAN, regval);
 
   /* Wait until the PHY is again IDLE */
 
@@ -2156,9 +2156,9 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
 
   /* Enable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Verify tht we can read the PHYID register */
 
@@ -2303,7 +2303,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
 
   /* Setup the EMAC link speed */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCFGR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCFGR);
   regval &= (EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
 
   if (((advertise & lpa) & MII_ADVERTISE_100BASETXFULL) != 0)
@@ -2331,28 +2331,28 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
     }
 #endif
 
-  sam_putreg(priv, SAM_EMAC0_NCFGR, regval);
+  sam_putreg(priv, SAM_EMAC_NCFGR, regval);
 
   /* Select RMII/MII */
 
-  regval = sam_getreg(priv, SAM_EMAC0_USRIO);
-#ifdef CONFIG_SAMA5_EMAC0_RMII
+  regval = sam_getreg(priv, SAM_EMAC_USRIO);
+#ifdef CONFIG_SAMA5_EMAC_RMII
   regval |= EMAC_USRIO_RMII;
-#else /* defined(CONFIG_SAMA5_EMAC0_MII) */
+#else /* defined(CONFIG_SAMA5_EMAC_MII) */
   regval &= ~EMAC_USRIO_RMII;
 #endif
 
   /* Enable the transceiver clock */
 
   regval |=  EMAC_USRIO_CLKEN;
-  sam_putreg(priv, SAM_EMAC0_USRIO, regval);
+  sam_putreg(priv, SAM_EMAC_USRIO, regval);
 
 errout:
   /* Disable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval &= ~EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
   return ret;
 }
 
@@ -2380,9 +2380,9 @@ static bool sam_linkup(struct sam_emac_s *priv)
 
   /* Enable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
   if (ret < 0)
@@ -2399,14 +2399,14 @@ static bool sam_linkup(struct sam_emac_s *priv)
 
   /* Re-configure Link speed */
 
-  ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC0_PHYSR, &physr);
+  ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &physr);
   if (ret < 0)
     {
       nlldbg("ERROR: Failed to read PHYSR: %d\n", ret);
       goto errout;
     }
 
-  regval = sam_getreg(priv, SAM_EMAC0_NCFGR);
+  regval = sam_getreg(priv, SAM_EMAC_NCFGR);
   regval &= ~(EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
 
   if ((msr & MII_MSR_100BASETXFULL) != 0 && PHYSR_IS100FDX(physr))
@@ -2436,7 +2436,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
     }
 #endif
 
-  sam_putreg(priv, SAM_EMAC0_NCFGR, regval);
+  sam_putreg(priv, SAM_EMAC_NCFGR, regval);
 
   /* Start the EMAC transfers */
 
@@ -2446,9 +2446,9 @@ static bool sam_linkup(struct sam_emac_s *priv)
 errout:
   /* Disable management port */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval &= ~EMAC_NCR_MPE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   return linkup;
 }
@@ -2475,7 +2475,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
 
   /* Configure PHY clocking */
 
-  regval = sam_getreg(priv, SAM_EMAC0_NCFGR);
+  regval = sam_getreg(priv, SAM_EMAC_NCFGR);
   regval &= ~EMAC_NCFGR_CLK_MASK;
 
   mck = BOARD_MCK_FREQUENCY;
@@ -2501,11 +2501,11 @@ static int sam_phyinit(struct sam_emac_s *priv)
       regval |= EMAC_NCFGR_CLK_DIV8;  /* MCK divided by 8 (MCK up to 20 MHz) */
     }
 
-  sam_putreg(priv, SAM_EMAC0_NCFGR, regval);
+  sam_putreg(priv, SAM_EMAC_NCFGR, regval);
 
   /* Check the PHY Address */
 
-  priv->phyaddr = CONFIG_SAMA5_EMAC0_PHYADDR;
+  priv->phyaddr = CONFIG_SAMA5_EMAC_PHYADDR;
   ret = sam_phyfind(priv, &priv->phyaddr);
   if (ret < 0)
     {
@@ -2513,7 +2513,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
       return ret;
     }
 
-  if (priv->phyaddr != CONFIG_SAMA5_EMAC0_PHYADDR)
+  if (priv->phyaddr != CONFIG_SAMA5_EMAC_PHYADDR)
     {
       sam_phyreset(priv);
     }
@@ -2542,16 +2542,16 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
   /* Configure PIO pins to support EMAC */
   /* Configure EMAC PIO pins common to both MII and RMII */
 
-  sam_configpio(PIO_EMAC0_TX0);
-  sam_configpio(PIO_EMAC0_TX1);
-  sam_configpio(PIO_EMAC0_RX0);
-  sam_configpio(PIO_EMAC0_RX1);
-  sam_configpio(PIO_EMAC0_TXEN);
-  sam_configpio(PIO_EMAC0_CRSDV);
-  sam_configpio(PIO_EMAC0_RXER);
-  sam_configpio(PIO_EMAC0_REFCK);
-  sam_configpio(PIO_EMAC0_MDC);
-  sam_configpio(PIO_EMAC0_MDIO);
+  sam_configpio(PIO_EMAC_TX0);
+  sam_configpio(PIO_EMAC_TX1);
+  sam_configpio(PIO_EMAC_RX0);
+  sam_configpio(PIO_EMAC_RX1);
+  sam_configpio(PIO_EMAC_TXEN);
+  sam_configpio(PIO_EMAC_CRSDV);
+  sam_configpio(PIO_EMAC_RXER);
+  sam_configpio(PIO_EMAC_REFCK);
+  sam_configpio(PIO_EMAC_MDC);
+  sam_configpio(PIO_EMAC_MDIO);
 }
 
 /****************************************************************************
@@ -2581,16 +2581,16 @@ static void sam_txreset(struct sam_emac_s *priv)
 
   /* Disable TX */
 
-  regval = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval = sam_getreg(priv, SAM_EMAC_NCR);
   regval &= ~EMAC_NCR_TE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Configure the TX descriptors. */
 
   priv->txhead = 0;
   priv->txtail = 0;
 
-  for (ndx = 0; ndx < CONFIG_SAMA5_EMAC0_NTXBUFFERS; ndx++)
+  for (ndx = 0; ndx < CONFIG_SAMA5_EMAC_NTXBUFFERS; ndx++)
   {
     bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE]));
 
@@ -2603,19 +2603,19 @@ static void sam_txreset(struct sam_emac_s *priv)
 
   /* Mark the final descriptor in the list */
 
-  txdesc[CONFIG_SAMA5_EMAC0_NTXBUFFERS - 1].status =
+  txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS - 1].status =
     EMACTXD_STA_USED | EMACTXD_STA_WRAP;
 
   /* Flush the entire TX descriptor table to RAM */
 
   cp15_clean_dcache((uintptr_t)txdesc,
                     (uintptr_t)txdesc +
-                    CONFIG_SAMA5_EMAC0_NTXBUFFERS * sizeof(struct emac_txdesc_s));
+                    CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s));
 
   /* Set the Transmit Buffer Queue Pointer Register */
 
   physaddr = sam_physramaddr((uintptr_t)txdesc);
-  sam_putreg(priv, SAM_EMAC0_TBQP, physaddr);
+  sam_putreg(priv, SAM_EMAC_TBQP, physaddr);
 }
 
 /****************************************************************************
@@ -2645,14 +2645,14 @@ static void sam_rxreset(struct sam_emac_s *priv)
 
   /* Disable RX */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval &= ~EMAC_NCR_RE;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Configure the RX descriptors. */
 
   priv->rxndx = 0;
-  for (ndx = 0; ndx < CONFIG_SAMA5_EMAC0_NRXBUFFERS; ndx++)
+  for (ndx = 0; ndx < CONFIG_SAMA5_EMAC_NRXBUFFERS; ndx++)
   {
     bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE]));
     DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0);
@@ -2668,18 +2668,18 @@ static void sam_rxreset(struct sam_emac_s *priv)
 
   /* Mark the final descriptor in the list */
 
-  rxdesc[CONFIG_SAMA5_EMAC0_NRXBUFFERS - 1].addr |= EMACRXD_ADDR_WRAP;
+  rxdesc[CONFIG_SAMA5_EMAC_NRXBUFFERS - 1].addr |= EMACRXD_ADDR_WRAP;
 
   /* Flush the entire RX descriptor table to RAM */
 
   cp15_clean_dcache((uintptr_t)rxdesc,
                     (uintptr_t)rxdesc +
-                    CONFIG_SAMA5_EMAC0_NRXBUFFERS * sizeof(struct emac_rxdesc_s));
+                    CONFIG_SAMA5_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s));
 
   /* Set the Receive Buffer Queue Pointer Register */
 
   physaddr = sam_physramaddr((uintptr_t)rxdesc);
-  sam_putreg(priv, SAM_EMAC0_RBQP, physaddr);
+  sam_putreg(priv, SAM_EMAC_RBQP, physaddr);
 }
 
 /****************************************************************************
@@ -2704,7 +2704,7 @@ static void sam_emac_reset(struct sam_emac_s *priv)
 
   /* Disable all EMAC interrupts */
 
-  sam_putreg(priv, SAM_EMAC0_IDR, EMAC_INT_ALL);
+  sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
 
   /* Reset RX and TX logic */
 
@@ -2714,11 +2714,11 @@ static void sam_emac_reset(struct sam_emac_s *priv)
   /* Disable RX, TX, and statistics */
 
   regval = EMAC_NCR_TE | EMAC_NCR_RE | EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Disable clocking to the EMAC peripheral */
 
-  sam_emac0_disableclk();
+  sam_emac_disableclk();
 }
 
 /****************************************************************************
@@ -2754,11 +2754,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
            (uint32_t)dev->d_mac.ether_addr_octet[1] << 8 |
            (uint32_t)dev->d_mac.ether_addr_octet[2] << 16 |
            (uint32_t)dev->d_mac.ether_addr_octet[3] << 24;
-  sam_putreg(priv, SAM_EMAC0_SA1B, regval);
+  sam_putreg(priv, SAM_EMAC_SA1B, regval);
 
   regval = (uint32_t)dev->d_mac.ether_addr_octet[4] |
            (uint32_t)dev->d_mac.ether_addr_octet[5] << 8;
-  sam_putreg(priv, SAM_EMAC0_SA1T, regval);
+  sam_putreg(priv, SAM_EMAC_SA1T, regval);
 }
 
 /****************************************************************************
@@ -2785,37 +2785,37 @@ static int sam_emac_configure(struct sam_emac_s *priv)
 
   /* Enable clocking to the EMAC peripheral */
 
-  sam_emac0_enableclk();
+  sam_emac_enableclk();
 
   /* Disable TX, RX, interrupts, etc. */
 
-  sam_putreg(priv, SAM_EMAC0_NCR, 0);
-  sam_putreg(priv, SAM_EMAC0_IDR, EMAC_INT_ALL);
+  sam_putreg(priv, SAM_EMAC_NCR, 0);
+  sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
 
-  regval = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= EMAC_NCR_CLRSTAT;
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Clear all status bits in the receive status register. */
 
   regval = (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA);
-  sam_putreg(priv, SAM_EMAC0_RSR, regval);
+  sam_putreg(priv, SAM_EMAC_RSR, regval);
 
   /* Clear all status bits in the transmit status register */
 
   regval = (EMAC_TSR_UBR | EMAC_TSR_COL | EMAC_TSR_RLES | EMAC_TSR_BEX |
             EMAC_TSR_COMP | EMAC_TSR_UND);
-  sam_putreg(priv, SAM_EMAC0_TSR, regval);
+  sam_putreg(priv, SAM_EMAC_TSR, regval);
 
   /* Clear any pending interrupts */
 
-  (void)sam_getreg(priv, SAM_EMAC0_ISR);
+  (void)sam_getreg(priv, SAM_EMAC_ISR);
 
   /* Enable/disable the copy of data into the buffers, ignore broadcasts.
    * Don't copy FCS.
    */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCFGR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCFGR);
   regval |= (EMAC_NCFGR_DRFCS | EMAC_NCFGR_PAE);
 
 #ifdef CONFIG_NET_PROMISCUOUS
@@ -2824,13 +2824,13 @@ static int sam_emac_configure(struct sam_emac_s *priv)
   regval &= ~EMAC_NCFGR_CAF;
 #endif
 
-#ifdef CONFIG_SAMA5_EMAC0_NBC
+#ifdef CONFIG_SAMA5_EMAC_NBC
   regval |=  EMAC_NCFGR_NBC;
 #else
   regval &= ~EMAC_NCFGR_NBC;
 #endif
 
-  sam_putreg(priv, SAM_EMAC0_NCFGR, regval);
+  sam_putreg(priv, SAM_EMAC_NCFGR, regval);
 
   /* Reset TX and RX */
 
@@ -2839,16 +2839,16 @@ static int sam_emac_configure(struct sam_emac_s *priv)
 
   /* Enable Rx and Tx, plus the stats register. */
 
-  regval  = sam_getreg(priv, SAM_EMAC0_NCR);
+  regval  = sam_getreg(priv, SAM_EMAC_NCR);
   regval |= (EMAC_NCR_RE | EMAC_NCR_TE | EMAC_NCR_WESTAT);
-  sam_putreg(priv, SAM_EMAC0_NCR, regval);
+  sam_putreg(priv, SAM_EMAC_NCR, regval);
 
   /* Setup the interrupts for TX events, RX events, and error events */
 
   regval = (EMAC_INT_RCOMP | EMAC_INT_RXUBR | EMAC_INT_TUND | EMAC_INT_RLE |
             EMAC_INT_TXERR | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
             EMAC_INT_PFR | EMAC_INT_PTZ);
-  sam_putreg(priv, SAM_EMAC0_IER, regval);
+  sam_putreg(priv, SAM_EMAC_IER, regval);
   return OK;
 }
 
@@ -2925,16 +2925,16 @@ int sam_emac_initialize(void)
    * the interface is in the 'up' state.
    */
 
-  ret = irq_attach(SAM_IRQ_EMAC0, sam_emac_interrupt);
+  ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt);
   if (ret < 0)
     {
-      nlldbg("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC0);
+      nlldbg("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
       goto errout_with_buffers;
     }
 
   /* Enable clocking to the EMAC peripheral (just for sam_ifdown()) */
 
-  sam_emac0_enableclk();
+  sam_emac_enableclk();
 
   /* Put the interface in the down state (disabling clocking again). */
 
@@ -2965,4 +2965,4 @@ errout:
   return ret;
 }
 
-#endif /* CONFIG_NET && CONFIG_SAMA5_EMAC0 */
+#endif /* CONFIG_NET && CONFIG_SAMA5_EMAC */
diff --git a/nuttx/arch/arm/src/sama5/sam_ethernet.c b/nuttx/arch/arm/src/sama5/sam_ethernet.c
index 1a8f15f4c..d9696eeed 100644
--- a/nuttx/arch/arm/src/sama5/sam_ethernet.c
+++ b/nuttx/arch/arm/src/sama5/sam_ethernet.c
@@ -109,7 +109,7 @@ static inline void up_gmac_initialize(void)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SAMA5_EMAC0
+#ifdef CONFIG_SAMA5_EMAC
 static inline void up_emac_initialize(void)
 {
   int ret;
@@ -162,4 +162,4 @@ void up_netinitialize(void)
 #endif
 }
 
-#endif /* CONFIG_NET && CONFIG_SAMA5_EMAC0 */
+#endif /* CONFIG_NET */
diff --git a/nuttx/arch/arm/src/sama5/sam_ethernet.h b/nuttx/arch/arm/src/sama5/sam_ethernet.h
index ac6cc674e..adb85c4a6 100644
--- a/nuttx/arch/arm/src/sama5/sam_ethernet.h
+++ b/nuttx/arch/arm/src/sama5/sam_ethernet.h
@@ -60,11 +60,11 @@
 #  undef CONFIG_SAMA5_GMAC_ISETH0
 #endif
 
-#ifndef CONFIG_SAMA5_EMAC0
-#  undef CONFIG_SAMA5_EMAC0_ISETH0
+#ifndef CONFIG_SAMA5_EMAC
+#  undef CONFIG_SAMA5_EMAC_ISETH0
 #endif
 
-#if defined(CONFIG_SAMA5_GMAC_ISETH0) && defined(CONFIG_SAMA5_EMAC0_ISETH0)
+#if defined(CONFIG_SAMA5_GMAC_ISETH0) && defined(CONFIG_SAMA5_EMAC_ISETH0)
 #  error GMAC and EMAC cannot both be ETH0
 #endif
 
@@ -94,7 +94,7 @@
 #  endif
 #endif
 
-#if defined(CONFIG_SAMA5_EMAC0_ISETH0)
+#if defined(CONFIG_SAMA5_EMAC_ISETH0)
 #  if defined(CONFIG_ETH0_PHY_DM9161)
 #    define SAMA5_EMAC_PHY_DM9161 1
 #  elif defined(CONFIG_ETH0_PHY_LAN8700)
@@ -106,7 +106,7 @@
 #  else
 #    error ETH0 PHY unrecognized
 #  endif
-#elif defined(CONFIG_SAMA5_EMAC0)
+#elif defined(CONFIG_SAMA5_EMAC)
 #  if defined(CONFIG_ETH1_PHY_DM9161)
 #    define SAMA5_EMAC_PHY_DM9161 1
 #  elif defined(CONFIG_ETH1_PHY_LAN8700)
@@ -172,7 +172,7 @@ int sam_gmac_initialize(void);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SAMA5_EMAC0
+#ifdef CONFIG_SAMA5_EMAC
 int sam_emac_initialize(void);
 #endif
 
diff --git a/nuttx/arch/arm/src/sama5/sam_isi.c b/nuttx/arch/arm/src/sama5/sam_isi.c
index d764109d0..e013e72a9 100644
--- a/nuttx/arch/arm/src/sama5/sam_isi.c
+++ b/nuttx/arch/arm/src/sama5/sam_isi.c
@@ -180,4 +180,4 @@ int sam_isi_initialize(void)
 #warning Missing logic
 }
 
-#endif /* CONFIG_SAMA5_ISI && CONFIG_SAMA5_EMAC0 */
+#endif /* CONFIG_SAMA5_ISI */
diff --git a/nuttx/arch/arm/src/sama5/sam_pck.c b/nuttx/arch/arm/src/sama5/sam_pck.c
index 78ec36331..55043fd4d 100644
--- a/nuttx/arch/arm/src/sama5/sam_pck.c
+++ b/nuttx/arch/arm/src/sama5/sam_pck.c
@@ -238,4 +238,4 @@ void sam_pck_enable(enum pckid_e pckid, bool enable)
   putreg32(regval, regaddr);
 }
 
-#endif /* CONFIG_SAMA5_ISI && CONFIG_SAMA5_EMAC0 */
+#endif /* CONFIG_SAMA5_ISI */
diff --git a/nuttx/arch/arm/src/sama5/sama5d3x_periphclks.h b/nuttx/arch/arm/src/sama5/sama5d3x_periphclks.h
index fa6f60897..2d2fe7c3e 100644
--- a/nuttx/arch/arm/src/sama5/sama5d3x_periphclks.h
+++ b/nuttx/arch/arm/src/sama5/sama5d3x_periphclks.h
@@ -91,7 +91,7 @@
 #define sam_uhphs_enableclk()      sam_enableperiph1(SAM_PID_UHPHS)
 #define sam_udphs_enableclk()      sam_enableperiph1(SAM_PID_UDPHS)
 #define sam_gmac_enableclk()       sam_enableperiph1(SAM_PID_GMAC)
-#define sam_emac0_enableclk()      sam_enableperiph1(SAM_PID_EMAC0)
+#define sam_emac_enableclk()       sam_enableperiph1(SAM_PID_EMAC)
 #define sam_lcdc_enableclk()       sam_enableperiph1(SAM_PID_LCDC)
 #define sam_isi_enableclk()        sam_enableperiph1(SAM_PID_ISI)
 #define sam_ssc0_enableclk()       sam_enableperiph1(SAM_PID_SSC0)
@@ -141,7 +141,7 @@
 #define sam_uhphs_disableclk()     sam_disableperiph1(SAM_PID_UHPHS)
 #define sam_udphs_disableclk()     sam_disableperiph1(SAM_PID_UDPHS)
 #define sam_gmac_disableclk()      sam_disableperiph1(SAM_PID_GMAC)
-#define sam_emac0_disableclk()     sam_disableperiph1(SAM_PID_EMAC0)
+#define sam_emac_disableclk()      sam_disableperiph1(SAM_PID_EMAC)
 #define sam_lcdc_disableclk()      sam_disableperiph1(SAM_PID_LCDC)
 #define sam_isi_disableclk()       sam_disableperiph1(SAM_PID_ISI)
 #define sam_ssc0_disableclk()      sam_disableperiph1(SAM_PID_SSC0)