Need to set UART interrupt priority

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1854 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 52 insertions, 18 deletions

diff --git a/nuttx/arch/arm/src/str71x/str71x_eic.h b/nuttx/arch/arm/src/str71x/str71x_eic.h
index 1f1c7e3a2..3ceffacd2 100644
--- a/nuttx/arch/arm/src/str71x/str71x_eic.h
+++ b/nuttx/arch/arm/src/str71x/str71x_eic.h
@@ -157,7 +157,6 @@
 #define STR71X_EICSIR_SIPLMASK     (0x0000000f) /* Bits 0-3: Source interrupt priority level */

 #define STR71X_EICSIR_SIVMASK      (0xffff0000) /* Bits 16-31: Source interrupt vector */

 

-

 /************************************************************************************

  * Public Types

  ************************************************************************************/

diff --git a/nuttx/arch/arm/src/str71x/str71x_head.S b/nuttx/arch/arm/src/str71x/str71x_head.S
index fd7f263e7..5e57c4d9d 100644
--- a/nuttx/arch/arm/src/str71x/str71x_head.S
+++ b/nuttx/arch/arm/src/str71x/str71x_head.S
@@ -319,6 +319,10 @@ eicloop:
 	/* Shift the IRQ number to bits 16-31 and save the shifted IRQ
 	 * number as SIR[irqno].  This will appear as bits 0:15 in the
 	 * IVR during IRQ processing.
+	 *
+	 * NOTE that the initial priority is set to zero -- the current
+	 * interrupt priority (CIP) is always zero, so these interrupts
+	 * are all disabled.
 	 */
 
 	mov	\value, \irqno, lsl #16
diff --git a/nuttx/arch/arm/src/str71x/str71x_irq.c b/nuttx/arch/arm/src/str71x/str71x_irq.c
index 6abbd27d9..40bbd9889 100644
--- a/nuttx/arch/arm/src/str71x/str71x_irq.c
+++ b/nuttx/arch/arm/src/str71x/str71x_irq.c
@@ -75,19 +75,19 @@ uint32 *current_regs;
 
 void up_irqinitialize(void)
 {
+  /* Currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
   /* The bulk of IRQ initialization if performed in str71x_head.S, so we
-   * have very little to do here:
+   * have very little to do here -- basically just enabling interrupts;
+   *
+   * Enable IRQs (but not FIQs -- they aren't used)
    */
 
-  /* Enable IRQs (but not FIQs -- they aren't used) */
-
   putreg32(STR71X_EICICR_IRQEN, STR71X_EIC_ICR);
 
-  /* Currents_regs is non-NULL only while processing an interrupt */
-
-  current_regs = NULL;
-
-  /* Enable interrupts */
+  /* Enable global ARM interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
   irqrestore(SVC_MODE | PSR_F_BIT);
@@ -130,6 +130,13 @@ void up_enable_irq(int irq)
 
   if ((unsigned)irq < NR_IRQS)
     {
+      /* Check the IRQs priority.  the current interrupt priority (CIP) is
+       * always zero so the priority must be at least one for the IRQ to be
+       * truly enabled.
+       */
+ 
+      DEBUGASSERT(getreg32(STR71X_EIC_SIR(irq)) & STR71X_EICSIR_SIPLMASK != 0);
+
       /* Enable the IRQ by setting the associated bit in the IER register */
 
       reg32  = getreg32(STR71X_EIC_IER);
@@ -165,7 +172,6 @@ void up_maskack_irq(int irq)
       reg32  = getreg32(STR71X_EIC_IPR);
       reg32 |= (1 << irq);
       putreg32(reg32, STR71X_EIC_IPR);
-
     }
 }
 
@@ -182,11 +188,15 @@ int up_prioritize_irq(int irq, int priority)
   uint32 addr;
   uint32 reg32;
 
-  if ((unsigned)irq < NR_IRQS && priority < 16)
+  /* The current interrupt priority (CIP) is always zero, so a minimum prioriy
+   * of one is enforced to prevent disabling the interrupt.
+   */
+
+  if ((unsigned)irq < NR_IRQS && priority > 0 && priority < 16)
     {
       addr   = STR71X_EIC_SIR(irq);
       reg32  = getreg32(addr);
-      reg32 &= STR71X_EICSIR_SIPLMASK;
+      reg32 &= ~STR71X_EICSIR_SIPLMASK;
       reg32 |= priority;
       putreg32(reg32, addr);
       return OK;
diff --git a/nuttx/arch/arm/src/str71x/str71x_serial.c b/nuttx/arch/arm/src/str71x/str71x_serial.c
index 5617edab0..c803a7277 100644
--- a/nuttx/arch/arm/src/str71x/str71x_serial.c
+++ b/nuttx/arch/arm/src/str71x/str71x_serial.c
@@ -77,6 +77,12 @@
 #  undef HAVE_CONSOLE
 #endif
 
+#ifndef CONFIG_UART_PRI
+#  define CONFIG_UART_PRI 1
+#elif CONFIG_UART_PRI <= 1 && CONFIG_UART_PRI >15
+#  error "CONFIG_UART_PRI is out of range"
+#endif
+
 /* If we are not using the serial driver for the console, then we
  * still must provide some minimal implementation of up_putc().
  */
@@ -580,6 +586,10 @@ static int up_attach(struct uart_dev_s *dev)
         */
 
        up_enable_irq(priv->irq);
+
+       /* Set the uart interrupt priority (the default value is one) */
+
+       up_prioritize_irq(priv->irq, CONFIG_UART_PRI);
     }
   return ret;
 }
@@ -668,7 +678,8 @@ static int up_interrupt(int irq, void *context)
 
       /* Handle incoming, receive bytes (with or without timeout) */
 
-      if ((priv->sr & STR71X_UARTSR_RNE) != 0)
+      if ((priv->sr  & STR71X_UARTSR_RNE)  != 0 && /* Rx FIFO not empty */
+          (priv->ier & STR71X_UARTIER_RHF) != 0)   /* Rx FIFO half full int enabled */
         {
            /* Rx buffer not empty ... process incoming bytes */
 
@@ -678,7 +689,8 @@ static int up_interrupt(int irq, void *context)
 
       /* Handle outgoing, transmit bytes */
 
-      if ((priv->sr & STR71X_UARTSR_TF) == 0)
+      if ((priv->sr & STR71X_UARTSR_TF) == 0 &&   /* Tx FIFO not full */
+          (priv->ier & STR71X_UARTIER_THE) != 0)  /* Tx Half empty interrupt enabled */
         {
            /* Tx FIFO not full ... process outgoing bytes */
 
@@ -686,7 +698,8 @@ static int up_interrupt(int irq, void *context)
            handled = TRUE;
         }
     }
-    return OK;
+
+  return OK;
 }
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/src/str71x/str71x_timerisr.c b/nuttx/arch/arm/src/str71x/str71x_timerisr.c
index ad4565cb9..1777be159 100644
--- a/nuttx/arch/arm/src/str71x/str71x_timerisr.c
+++ b/nuttx/arch/arm/src/str71x/str71x_timerisr.c
@@ -55,6 +55,14 @@
  * Definitions
  ****************************************************************************/
 
+/* Configuration */
+
+#ifndef CONFIG_TIM_PRI
+#  define CONFIG_TIM_PRI 1
+#elif CONFIG_TIM_PRI <= 1 && CONFIG_TIM_PRI >15
+#  error "CONFIG_TIM_PRI is out of range"
+#endif
+
 /* The desired timer interrupt frequency is provided by the definition
  * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
  * system clock ticks per second.  That value is a user configurable setting
@@ -189,9 +197,9 @@ void up_timerinit(void)
   putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR);
   putreg16(0xfffc, STR71X_TIMER0_CNTR);
 
-  /* Set the IRQ interrupt priority */
+  /* Set the timer interrupt priority */
 
-  up_prioritize_irq(STR71X_IRQ_SYSTIMER, 1);
+  up_prioritize_irq(STR71X_IRQ_SYSTIMER, CONFIG_TIM_PRI);
 
   /* Attach the timer interrupt vector */
 
diff --git a/nuttx/arch/arm/src/str71x/str71x_uart.h b/nuttx/arch/arm/src/str71x/str71x_uart.h
index eced989f0..d3018586f 100644
--- a/nuttx/arch/arm/src/str71x/str71x_uart.h
+++ b/nuttx/arch/arm/src/str71x/str71x_uart.h
@@ -161,7 +161,7 @@
 #define STR71X_UARTSR_PERR          (0x0008) /* Bit 3: Parity error */

 #define STR71X_UARTSR_FRERROR       (0x0010) /* Bit 4: Frame error */

 #define STR71X_UARTSR_OVERRUN       (0x0020) /* Bit 5: Overrun error */

-#define STR71X_UARTSR_TIMEOUTNE     (0x0040) /* Bit 6: Time out not empty*/

+#define STR71X_UARTSR_TIMEOUTNE     (0x0040) /* Bit 6: Time out not empty */

 #define STR71X_UARTSR_TIMEOUTIDLE   (0x0080) /* Bit 7: Timeout out idle */

 #define STR71X_UARTSR_RHF           (0x0100) /* Bit 8: Rx half full */

 #define STR71X_UARTSR_TF            (0x0200) /* Bit 9: Tx full */