More naming changes associated with earlier renaming of LP17xx up_spiinitialize; LPC178x SSP support; Open1788 SSP and touchscreen support

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5811 42af7a65-404d-4744-a932-0658087f49c3

3 files changed, 123 insertions, 12 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
index cf2620ebe..e584adad6 100755
--- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
@@ -312,15 +312,15 @@
 #define IOCON_FUNC_MASK             (7 << IOCON_FUNC_SHIFT)
 #define IOCON_MODE_SHIFT            (3)   /* Bits 3-4: Type D,A,W */
 #define IOCON_MODE_MASK             (3 << IOCON_MODE_SHIFT )
-#define IOCON_HYS_SHIFT             (5)   /* Bit 5: Type D,W  */
+#define IOCON_HYS_SHIFT             (5)   /* Bit 5: Type D,W */
 #define IOCON_HYS_MASK              (1 << IOCON_HYS_SHIFT)
-#define IOCON_INV_SHIFT             (6)   /* Bit 6: Typ D,A,I,W  */
+#define IOCON_INV_SHIFT             (6)   /* Bit 6: Type D,A,I,W */
 #define IOCON_INV_MASK              (1 << IOCON_INV_SHIFT)
 #define IOCON_ADMODE_SHIFT          (7)   /* Bit 7: Type A */
 #define IOCON_ADMODE_MASK           (1 << IOCON_ADMODE_SHIFT)
 #define IOCON_FILTER_SHIFT          (8)   /* Bit 8: Type A */
 #define IOCON_FILTER_MASK           (1 << IOCON_FILTER_SHIFT)
-#define IOCON_SLEW_SHIFT            (9)   /* Bit 9: Type W*/
+#define IOCON_SLEW_SHIFT            (9)   /* Bit 9: Type W */
 #define IOCON_SLEW_MASK             (1 << IOCON_SLEW_SHIFT)
 #define IOCON_HIDRIVE_SHIFT         (9)   /* Bit 9: Type I */
 #define IOCON_HIDRIVE_MASK          (1 << IOCON_HIDRIVE_SHIFT)
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
index a5d07f11d..cfe940614 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -193,7 +193,7 @@
 #define GPIO_IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3  */
 #define GPIO_IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
 
-#define GPIO_IOCON_MASK       (0x00FF0000)
+#define GPIO_IOCON_MASK       (0x00ff0000)
 #  define GPIO_HYSTERESIS     (1 << 16) /* Bit 16: HYSTERESIS: 0-Disable, 1-Enabled */
 #  define GPIO_INVERT         (1 << 17) /* Bit 17: Input: 0-Not Inverted, 1-Inverted */
 #  define GPIO_SLEW           (1 << 18) /* Bit 18: Rate Control: 0-Standard mode, 1-Fast mode */
@@ -259,7 +259,7 @@
 #define GPIO_VALUE_ONE       GPIO_VALUE
 #define GPIO_VALUE_ZERO      (0)
 
-/* Port number:    PPP (0-5) */
+/* Port number: PPP (0-5) */
 
 #define GPIO_PORT_SHIFT      (5)         /* Bit 5-7:  Port number */
 #define GPIO_PORT_MASK       (7 << GPIO_PORT_SHIFT)
@@ -272,7 +272,7 @@
 
 #define GPIO_NPORTS          6
 
-/* Pin number:     NNNNN (0-31) */
+/* Pin number: NNNNN (0-31) */
 
 #define GPIO_PIN_SHIFT       0        /* Bits 0-4: GPIO number: 0-31 */
 #define GPIO_PIN_MASK        (31 << GPIO_PIN_SHIFT)
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c
index 81b182e6c..3c9a51904 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c
@@ -58,7 +58,8 @@
 #include "lpc17_gpio.h"
 #include "lpc17_ssp.h"
 
-#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
+#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) || \
+    defined(CONFIG_LPC17_SSP2)
 
 /****************************************************************************
  * Definitions
@@ -91,6 +92,7 @@
 #endif
 
 /* SSP Clocking *************************************************************/
+#if defined(LPC176x)
 /* The CPU clock by 1, 2, 4, or 8 to get the SSP peripheral clock (SSP_CLOCK).
  * SSP_CLOCK may be further divided by 2-254 to get the SSP clock.  If we
  * want a usable range of 4KHz to 25MHz for the SSP, then:
@@ -102,12 +104,22 @@
  * use the CCLK undivided to get the SSP_CLOCK.
  */
 
-#if LPC17_CCLK > 100000000
-#  error "CCLK <= 100,000,000 assumed"
-#endif
+#  if LPC17_CCLK > 100000000
+#    error "CCLK <= 100,000,000 assumed"
+# endif
+
+#  define SSP_PCLKSET_DIV    SYSCON_PCLKSEL_CCLK
+#  define SSP_CLOCK          LPC17_CCLK
+
+/* All peripherals are clocked by the same peripheral clock in the LPC178x
+ * family.
+ */
+
+#elif defined(LPC178x)
 
-#define SSP_PCLKSET_DIV    SYSCON_PCLKSEL_CCLK
-#define SSP_CLOCK          LPC17_CCLK
+#  define SSP_CLOCK          BOARD_PCLK_FREQUENCY
+
+#endif
 
 /****************************************************************************
  * Private Types
@@ -161,6 +173,9 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void);
 #ifdef CONFIG_LPC17_SSP1
 static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void);
 #endif
+#ifdef CONFIG_LPC17_SSP2
+static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void);
+#endif
 
 /****************************************************************************
  * Private Data
@@ -234,6 +249,40 @@ static struct lpc17_sspdev_s g_ssp1dev =
 }; 
 #endif /* CONFIG_LPC17_SSP1 */
 
+#ifdef CONFIG_LPC17_SSP2
+static const struct spi_ops_s g_spi2ops =
+{
+#ifndef CONFIG_SPI_OWNBUS
+  .lock              = ssp_lock,
+#endif
+  .select            = lpc17_ssp2select,   /* Provided externally */
+  .setfrequency      = ssp_setfrequency,
+  .setmode           = ssp_setmode,
+  .setbits           = ssp_setbits,
+  .status            = lpc17_ssp2status,   /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+  .cmddata           = lpc17_ssp2cmddata,  /* Provided externally */
+#endif
+  .send              = ssp_send,
+  .sndblock          = ssp_sndblock,
+  .recvblock         = ssp_recvblock,
+#ifdef CONFIG_SPI_CALLBACK
+  .registercallback  = lpc17_ssp2register, /* Provided externally */
+#else
+  .registercallback  = 0,                  /* Not implemented */
+#endif
+};
+
+static struct lpc17_sspdev_s g_ssp2dev =
+{
+  .spidev            = { &g_spi2ops },
+  .sspbase           = LPC17_SSP2_BASE,
+#ifdef CONFIG_LPC17_SSP_INTERRUPTS
+  .sspirq            = LPC17_IRQ_SSP2,
+#endif
+}; 
+#endif /* CONFIG_LPC17_SSP2 */
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
@@ -741,10 +790,12 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void)
 
   /* Configure clocking */
 
+#ifdef LPC176x
   regval  = getreg32(LPC17_SYSCON_PCLKSEL1);
   regval &= ~SYSCON_PCLKSEL1_SSP0_MASK;
   regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT);
   putreg32(regval, LPC17_SYSCON_PCLKSEL1);
+#endif
 
   /* Enable peripheral clocking to SSP0 */
 
@@ -793,10 +844,12 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void)
 
   /* Configure clocking */
 
+#ifdef LPC176x
   regval  = getreg32(LPC17_SYSCON_PCLKSEL0);
   regval &= ~SYSCON_PCLKSEL0_SSP1_MASK;
   regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT);
   putreg32(regval, LPC17_SYSCON_PCLKSEL0);
+#endif
 
   /* Enable peripheral clocking to SSP0 and SSP1 */
 
@@ -810,6 +863,59 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void)
 #endif
 
 /****************************************************************************
+ * Name: lpc17_ssp2initialize
+ *
+ * Description:
+ *   Initialize the SSP2
+ *
+ * Input Parameter:
+ *   None
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC17_SSP2
+static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Configure multiplexed pins as connected on the board.  Chip select
+   * pins must be configured by board-specific logic.  All SSP2 pins have
+   * multiple, alternative pin selection. Definitions in the board.h file
+   * must be provided to resolve the board-specific pin configuration like:
+   *
+   * #define GPIO_SSP2_SCK GPIO_SSP2_SCK_1
+   */
+
+  flags = irqsave();
+  lpc17_configgpio(GPIO_SSP2_SCK);
+  lpc17_configgpio(GPIO_SSP2_MISO);
+  lpc17_configgpio(GPIO_SSP2_MOSI);
+
+  /* Configure clocking */
+
+#ifdef LPC176x
+  regval  = getreg32(LPC17_SYSCON_PCLKSEL0);
+  regval &= ~SYSCON_PCLKSEL0_SSP2_MASK;
+  regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP2_SHIFT);
+  putreg32(regval, LPC17_SYSCON_PCLKSEL0);
+#endif
+
+  /* Enable peripheral clocking to SSP0 and SSP1 */
+
+  regval  = getreg32(LPC17_SYSCON_PCONP);
+  regval |= SYSCON_PCONP_PCSSP2;
+  putreg32(regval, LPC17_SYSCON_PCONP);
+  irqrestore(flags);
+
+  return &g_ssp2dev;
+}
+#endif
+
+/****************************************************************************
  * Public Functions
  ****************************************************************************/
 
@@ -847,6 +953,11 @@ FAR struct spi_dev_s *lpc17_sspinitialize(int port)
       priv = lpc17_ssp1initialize();
       break;
 #endif
+#ifdef CONFIG_LPC17_SSP2
+    case 2:
+      priv = lpc17_ssp2initialize();
+      break;
+#endif
     default:
       return NULL;
     }