diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-05-15 22:26:02 +0000 |
---|---|---|
committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-05-15 22:26:02 +0000 |
commit | 8debfb89c5be818e19566125dad5ef88c3b62326 (patch) | |
tree | 4dac6877ce82220eb6c3c8d9619877ae9a041682 /nuttx/arch | |
parent | 8fb3d0130db14010249d2923c1c25e49110108c6 (diff) | |
download | px4-nuttx-8debfb89c5be818e19566125dad5ef88c3b62326.tar.gz px4-nuttx-8debfb89c5be818e19566125dad5ef88c3b62326.tar.bz2 px4-nuttx-8debfb89c5be818e19566125dad5ef88c3b62326.zip |
More PIC32 header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3614 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch')
-rwxr-xr-x | nuttx/arch/mips/src/pic32mx/chip.h | 136 | ||||
-rwxr-xr-x | nuttx/arch/mips/src/pic32mx/pic32mx-cm.h | 140 | ||||
-rwxr-xr-x | nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h | 114 | ||||
-rwxr-xr-x | nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h | 94 | ||||
-rwxr-xr-x | nuttx/arch/mips/src/pic32mx/pic32mx-ic.h | 166 | ||||
-rwxr-xr-x | nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h | 31 | ||||
-rwxr-xr-x | nuttx/arch/mips/src/pic32mx/pic32mx-oc.h | 211 |
7 files changed, 810 insertions, 82 deletions
diff --git a/nuttx/arch/mips/src/pic32mx/chip.h b/nuttx/arch/mips/src/pic32mx/chip.h index 3c4883baf..0dac54c2d 100755 --- a/nuttx/arch/mips/src/pic32mx/chip.h +++ b/nuttx/arch/mips/src/pic32mx/chip.h @@ -56,18 +56,18 @@ # define CHIP_PROGFLASH_KB 32
# define CHIP_DATAMEM_KB 8
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 0
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -80,18 +80,18 @@ # define CHIP_PROGFLASH_KB 64
# define CHIP_DATAMEM_KB 16
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 0
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -104,18 +104,18 @@ # define CHIP_PROGFLASH_KB 128
# define CHIP_DATAMEM_KB 16
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 0
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -128,18 +128,18 @@ # define CHIP_PROGFLASH_KB 128
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -152,18 +152,18 @@ # define CHIP_PROGFLASH_KB 256
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -176,18 +176,18 @@ # define CHIP_PROGFLASH_KB 512
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -200,18 +200,18 @@ # define CHIP_PROGFLASH_KB 128
# define CHIP_DATAMEM_KB 16
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 0
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -224,18 +224,18 @@ # define CHIP_PROGFLASH_KB 128
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -248,18 +248,18 @@ # define CHIP_PROGFLASH_KB 256
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -272,18 +272,18 @@ # define CHIP_PROGFLASH_KB 512
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 0
-# define CHIP_VREG
+# define CHIP_CVR
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -296,18 +296,18 @@ # define CHIP_PROGFLASH_KB 32
# define CHIP_DATAMEM_KB 8
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 0
# define CHIP_NUSBDMACHAN 2
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -320,18 +320,18 @@ # define CHIP_PROGFLASH_KB 128
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 2
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -344,18 +344,18 @@ # define CHIP_PROGFLASH_KB 256
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 2
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -368,18 +368,18 @@ # define CHIP_PROGFLASH_KB 512
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 2
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -392,18 +392,18 @@ # define CHIP_PROGFLASH_KB 128
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 2
-# define CHIP_VREG
+# define CHIP_CVR
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -416,18 +416,18 @@ # define CHIP_PROGFLASH_KB 256
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 2
-# define CHIP_VREG
+# define CHIP_CVR
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
@@ -440,18 +440,18 @@ # define CHIP_PROGFLASH_KB 512
# define CHIP_DATAMEM_KB 32
# define CHIP_NTIMERS 5
-# define CHIP_NCAPTURE 5
-# define CHIP_NCOMPARE 5
+# define CHIP_NIC 5
+# define CHIP_NOC 5
# define CHIP_NDMACH 4
# define CHIP_NUSBDMACHAN 2
-# define CHIP_VREG
+# define CHIP_CVR
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
-# define CHIP_NCOMPARATORS 2
+# define CHIP_NCM 2
# define CHIP_PMP
# define CHIP_PSP
# define CHIP_JTAH
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-cm.h b/nuttx/arch/mips/src/pic32mx/pic32mx-cm.h new file mode 100755 index 000000000..9268089c0 --- /dev/null +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-cm.h @@ -0,0 +1,140 @@ +/************************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-cm.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "pic32mx-memorymap.h"
+
+#if CHIP_NCM > 0
+
+/************************************************************************************
+ * Pre-Processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define PIC32MX_CM_CON_OFFSET 0x0000 /* Comparator control register */
+#define PIC32MX_CM_CONCLR_OFFSET 0x0004 /* Comparator control clear register */
+#define PIC32MX_CM_CONSET_OFFSET 0x0008 /* Comparator control set register */
+#define PIC32MX_CM_CONINV_OFFSET 0x000c /* Comparator control invert register */
+#define PIC32MX_CM_STAT_OFFSET 0x0060 /* Comparator status register */
+#define PIC32MX_CM_STATCLR_OFFSET 0x0064 /* Comparator status clear register */
+#define PIC32MX_CM_STATSET_OFFSET 0x0068 /* Comparator status set register */
+#define PIC32MX_CM_STATINV_OFFSET 0x006c /* Comparator status invert register */
+
+/* Register Addresses ***************************************************************/
+
+#define PIC32MX_CM1_CON (PIC32MX_CM1_K1BASE+PIC32MX_CM_CON_OFFSET)
+#define PIC32MX_CM1_CONCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONCLR_OFFSET)
+#define PIC32MX_CM1_CONSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONSET_OFFSET)
+#define PIC32MX_CM1_CONINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONINV_OFFSET)
+
+#if CHIP_NCM > 0
+# define PIC32MX_CM2_CON (PIC32MX_CM2_K1BASE+PIC32MX_CM_CON_OFFSET)
+# define PIC32MX_CM2_CONCLR (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONCLR_OFFSET)
+# define PIC32MX_CM2_CONSET (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONSET_OFFSET)
+# define PIC32MX_CM2_CONINV (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONINV_OFFSET)
+#endif
+
+#define PIC32MX_CM_STAT (PIC32MX_CM_K1BASE+PIC32MX_CM_STAT_OFFSET)
+#define PIC32MX_CM_STATCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATCLR_OFFSET)
+#define PIC32MX_CM_STATSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATSET_OFFSET)
+#define PIC32MX_CM_STATINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATINV_OFFSET)
+
+/* Register Bit-Field Definitions ***************************************************/
+
+/* Comparator control register */
+
+#define CM_CON_CCH_SHIFT (0) /* Bits 0-1: Comparator negative input select */
+#define CM_CON_CCH_MASK (3 << CM_CON_CCH_SHIFT)
+# define CM_CON_CCH_CXINM (0 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN- */
+# define CM_CON_CCH_CXINP (1 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN+ */
+# define CM_CON_CCH_CYINP (2 << CM_CON_CCH_SHIFT) /* Inverting input connected to CyIN+ */
+# define CM_CON_CCH_IVREF (3 << CM_CON_CCH_SHIFT) /* Inverting input connected to IVREF */
+#define CM_CON_CREF (1 << 4) /* Bit 4: Comparator positive input configure */
+#define CM_CON_EVPOL_SHIFT (6) /* Bits 6-7: Interrupt event polarity select */
+#define CM_CON_EVPOL_MASK (3 << CM_CON_EVPOL_SHIFT)
+# define CM_CON_EVPOL_DISABLED (0 << CM_CON_EVPOL_SHIFT) /* Interrupt disabled */
+# define CM_CON_EVPOL_RISING (1 << CM_CON_EVPOL_SHIFT) /* Interrupt on low-to-high transition */
+# define CM_CON_EVPOL_FALLING (2 << CM_CON_EVPOL_SHIFT) /* Interrupt on high-to-low transition */
+# define CM_CON_EVPOL_BOTH (3 << CM_CON_EVPOL_SHIFT) /* Interrupt on a both transitions */
+#define CM_CON_COUT (1 << 8) /* Bit 8: Comparator output */
+#define CM_CON_CPOL (1 << 13) /* Bit 13: Comparator output inversion */
+#define CM_CON_COE (1 << 14) /* Bit 14: Comparator output enable */
+#define CM_CON_ON (1 << 15) /* Bit 15: Comparator ON */
+
+/* Comparator status register */
+
+#define CM_STAT_C1OUT (1 << 0) /* Bit 0: Comparator 1 output */
+#define CM_STAT_C2OUT (1 << 1) /* Bit 1: Comparator 2 output */
+#define CM_STAT_SIDL (1 << 13) /* Bit 13: Stop in idle control */
+#define CM_STAT_FRZ (1 << 14) /* Bit 14: Freeze control */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CHIP_NCM > 0 */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h b/nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h new file mode 100755 index 000000000..1383bfece --- /dev/null +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h @@ -0,0 +1,114 @@ +/************************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-cvr.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "pic32mx-memorymap.h"
+
+#ifdef CHIP_CVR
+
+/************************************************************************************
+ * Pre-Processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define PIC32MX_CVR_CON_OFFSET 0x0000 /* Comparator voltage reference control register */
+#define PIC32MX_CVR_CONCLR_OFFSET 0x0004 /* Comparator voltage reference control clear register */
+#define PIC32MX_CVR_CONSET_OFFSET 0x0008 /* Comparator voltage reference control set register */
+#define PIC32MX_CVR_CONINV_OFFSET 0x000c /* Comparator voltage reference control invert register */
+
+/* Register Addresses ***************************************************************/
+
+#define PIC32MX_CVR_CON (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CON_OFFSET)
+#define PIC32MX_CVR_CONCLR (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONCLR_OFFSET)
+#define PIC32MX_CVR_CONSET (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONSET_OFFSET)
+#define PIC32MX_CVR_CONINV (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONINV_OFFSET)
+
+/* Register Bit-Field Definitions ***************************************************/
+
+/* Comparator voltage reference control register */
+
+#define CVR_CON_CVR_SHIFT (0) /* Bits 0-3: CVREF value selection */
+#define CVR_CON_CVR_MASK (15 << CVR_CON_CVR_SHIFT)
+# define CVR_CON_CVR(n) ((n) << CVR_CON_CVR_SHIFT)
+#define CVR_CON_CVRSS (1 << 4) /* Bit 4: CVREF source selection */
+#define CVR_CON_CVRR (1 << 5) /* Bit 5: CVREF range selection */
+#define CVR_CON_CVROE (1 << 6) /* Bit 6: CVREFOUT enable */
+#define CVR_CON_BGSEL_SHIFT (8) /* Bits 8-9: Band gap reference source */
+#define CVR_CON_BGSEL_MASK (3 << CVR_CON_CVR_SHIFT)
+# define CVR_CON_BGSEL_1p2V (0 << CVR_CON_CVR_SHIFT) /* IVREF = 1.2V (nominal) */
+# define CVR_CON_BGSEL_0p6V (1 << CVR_CON_CVR_SHIFT) /* IVREF = 0.6V (nominal) */
+# define CVR_CON_BGSEL_0p2V (2 << CVR_CON_CVR_SHIFT) /* IVREF = 0.2V (nominal) */
+# define CVR_CON_BGSEL_VREF (3 << CVR_CON_CVR_SHIFT) /* VREF = VREF+ */
+#define CVR_CON_VREFSEL (1 << 10) /* Bit 10: Voltage reference select */
+#define CVR_CON_ON (1 << 15) /* Bit 15: Comparator voltage reference on */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CHIP_CVR */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h b/nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h new file mode 100755 index 000000000..8c8b8d787 --- /dev/null +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h @@ -0,0 +1,94 @@ +/************************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-ddp.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "pic32mx-memorymap.h"
+
+/************************************************************************************
+ * Pre-Processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define PIC32MX_DDP_CON_OFFSET 0x0000 /* Control Register for the Diagnostic Module */
+
+/* Register Addresses ***************************************************************/
+
+#define PIC32MX_DDP_CON (PIC32MX_DDP_K1BASE+PIC32MX_DDP_CON_OFFSET)
+
+/* See also the ICESEL, DEBUG, and DEBUG0 in the DEVCFG0 register */
+
+/* Register Bit-Field Definitions ***************************************************/
+
+/* Control Register for the Diagnostic Module */
+
+#define DDP_CON_TROEN (1 << 2) /* Bit 2: Trace output enable */
+#define DDP_CON_JTAGEN (1 << 3) /* Bit 3: JTAG port enable */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ic.h b/nuttx/arch/mips/src/pic32mx/pic32mx-ic.h new file mode 100755 index 000000000..88e62575a --- /dev/null +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ic.h @@ -0,0 +1,166 @@ +/************************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-ic.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "pic32mx-memorymap.h"
+
+#if CHIP_NIC > 0
+
+/************************************************************************************
+ * Pre-Processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define PIC32MX_IC_CON_OFFSET 0x0000 /* Input Capture X Control Register */
+#define PIC32MX_IC_CONCLR_OFFSET 0x0004 /* Input Capture X Control Set Register */
+#define PIC32MX_IC_CONSET_OFFSET 0x0008 /* Input Capture X Control Clear Register */
+#define PIC32MX_IC_CONINV_OFFSET 0x000c /* Input Capture X Control Invert Register */
+#define PIC32MX_IC_BUF_OFFSET 0x0010 /* Input Capture X Buffer Register */
+
+/* Register Addresses ***************************************************************/
+
+#define PIC32MX_IC_CON(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CON_OFFSET)
+#define PIC32MX_IC_CONCLR(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONCLR_OFFSET)
+#define PIC32MX_IC_CONSET(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONSET_OFFSET)
+#define PIC32MX_IC_CONINV(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONINV_OFFSET)
+#define PIC32MX_IC_BUF(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_BUF_OFFSET)
+
+#define PIC32MX_IC1_CON (PIC32MX_IC1_K1BASE+PIC32MX_IC_CON_OFFSET)
+#define PIC32MX_IC1_CONCLR (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
+#define PIC32MX_IC1_CONSET (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONSET_OFFSET)
+#define PIC32MX_IC1_CONINV (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONINV_OFFSET)
+#define PIC32MX_IC1_BUF (PIC32MX_IC1_K1BASE+PIC32MX_IC_BUF_OFFSET)
+
+#if CHIP_NIC > 1
+# define PIC32MX_IC2_CON (PIC32MX_IC2_K1BASE+PIC32MX_IC_CON_OFFSET)
+# define PIC32MX_IC2_CONCLR (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
+# define PIC32MX_IC2_CONSET (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONSET_OFFSET)
+# define PIC32MX_IC2_CONINV (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONINV_OFFSET)
+# define PIC32MX_IC2_BUF (PIC32MX_IC2_K1BASE+PIC32MX_IC_BUF_OFFSET)
+#endif
+
+#if CHIP_NIC > 2
+# define PIC32MX_IC3_CON (PIC32MX_IC3_K1BASE+PIC32MX_IC_CON_OFFSET)
+# define PIC32MX_IC3_CONCLR (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
+# define PIC32MX_IC3_CONSET (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONSET_OFFSET)
+# define PIC32MX_IC3_CONINV (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONINV_OFFSET)
+# define PIC32MX_IC3_BUF (PIC32MX_IC3_K1BASE+PIC32MX_IC_BUF_OFFSET)
+#endif
+
+#if CHIP_NIC > 3
+# define PIC32MX_IC4_CON (PIC32MX_IC4_K1BASE+PIC32MX_IC_CON_OFFSET)
+# define PIC32MX_IC4_CONCLR (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
+# define PIC32MX_IC4_CONSET (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONSET_OFFSET)
+# define PIC32MX_IC4_CONINV (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONINV_OFFSET)
+# define PIC32MX_IC4_BUF (PIC32MX_IC4_K1BASE+PIC32MX_IC_BUF_OFFSET)
+#endif
+
+#if CHIP_NIC > 4
+# define PIC32MX_IC5_CON (PIC32MX_IC5_K1BASE+PIC32MX_IC_CON_OFFSET)
+# define PIC32MX_IC5_CONCLR (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
+# define PIC32MX_IC5_CONSET (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONSET_OFFSET)
+# define PIC32MX_IC5_CONINV (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONINV_OFFSET)
+# define PIC32MX_IC5_BUF (PIC32MX_IC5_K1BASE+PIC32MX_IC_BUF_OFFSET)
+#endif
+
+/* Register Bit-Field Definitions ***************************************************/
+
+/* Input Capture X Control Register */
+
+#define IC_CON_ICI_SHIFT (0) /* Bits 0-2: Input Capture Mode Select */
+#define IC_CON_ICM_MASK (7 << IC_CON_ICI_SHIFT)
+# define IC_CON_ICM_DISABLE (0 << IC_CON_ICI_SHIFT) /* Capture disable mode */
+# define IC_CON_ICM_EDGE (1 << IC_CON_ICI_SHIFT) /* Edge detect mode */
+# define IC_CON_ICM_FALLING (2 << IC_CON_ICI_SHIFT) /* Every falling edge */
+# define IC_CON_ICM_RISING (3 << IC_CON_ICI_SHIFT) /* Every rising edge */
+# define IC_CON_ICM_4th (4 << IC_CON_ICI_SHIFT) /* Every fourth rising edge */
+# define IC_CON_ICM_16th (5 << IC_CON_ICI_SHIFT) /* Every sixteenth rising edge */
+# define IC_CON_ICM_TRIGGER (6 << IC_CON_ICI_SHIFT) /* Specified edge first and every edge thereafter */
+# define IC_CON_ICM_INTERRUPT (7 << IC_CON_ICI_SHIFT) /* Interrupt-only mode */
+#define IC_CON_ICBNE (1 << 3) /* Bit 3: Input Capture Buffer Not Empty Status */
+#define IC_CON_ICOV (1 << 4) /* Bit 4: Input Capture */
+#define IC_CON_ICI_SHIFT (5) /* Bits 5-6: Interrupt Control */
+#define IC_CON_ICI_MASK (3 << IC_CON_ICI_SHIFT)
+# define IC_CON_ICI_EVERY (0 << IC_CON_ICI_SHIFT) /* Interrupt every capture event */
+# define IC_CON_ICI_2ND (1 << IC_CON_ICI_SHIFT) /* Interrupt every 2nd capture event */
+# define IC_CON_ICI_3RD (2 << IC_CON_ICI_SHIFT) /* Interrupt every 3rd capture event */
+# define IC_CON_ICI_4TH (3 << IC_CON_ICI_SHIFT) /* Interrupt every 4th capture event */
+#define IC_CON_ICTMR (1 << 7) /* Bit 7: Timer Select */
+#define IC_CON_C32 (1 << 8) /* Bit 8: 32-bit Capture Select */
+#define IC_CON_FEDGE (1 << 9) /* Bit 9: First Capture Edge Select */
+#define IC_CON_SIDL (1 << 13) /* Bit 13: Stop in Idle Control */
+#define IC_CON_FRZ (1 << 14) /* Bit 14: Freeze in Debug Mode Control */
+#define IC_CON_ON (1 << 15) /* Bit 15: Input Capture Module Enable */
+
+/* Input Capture X Buffer Register -- 32-bit capture value */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CHIP_NIC > 0 */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h index 9188a2b26..061859806 100755 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h @@ -93,20 +93,21 @@ /* Input Capture 1-5 Register Base Addresses */
-# define PIC32MX_INCAP_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
-# define PIC32MX_INCAP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
-# define PIC32MX_INCAP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
-# define PIC32MX_INCAP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
-# define PIC32MX_INCAP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
-# define PIC32MX_INCAP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
+# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
+# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
+# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
+# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
+# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
+# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
/* Output Compare 1-5 Register Base Addresses */
-# define PIC32MX_OUTCMP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
-# define PIC32MX_OUTCMP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
-# define PIC32MX_OUTCMP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
-# define PIC32MX_OUTCMP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
-# define PIC32MX_OUTCMP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
+# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1))
+# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
+# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
+# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
+# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
+# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
/* I2C 1-2 Register Base Addresses */
@@ -133,11 +134,13 @@ /* Comparator Voltage Reference Register Base Addresses */
-# define PIC32MX_VREF_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
+# define PIC32MX_CVR_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
/* Comparator Register Base Addresses */
-# define PIC32MX_COMP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
+# define PIC32MX_CM_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
+# define PIC32MX_CM1_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
+# define PIC32MX_CM2_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a010)
/* Oscillator Control Register Base Addresses */
@@ -145,7 +148,7 @@ /* Programming and Diagnostics Register Base Addresses */
-# define PIC32MX_SYSCON_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
+# define PIC32MX_DDP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
/* FLASH Controller Register Base Addresses */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-oc.h b/nuttx/arch/mips/src/pic32mx/pic32mx-oc.h new file mode 100755 index 000000000..52f1bf2a6 --- /dev/null +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-oc.h @@ -0,0 +1,211 @@ +/************************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-oc.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "pic32mx-memorymap.h"
+
+#if CHIP_NOC > 0
+
+/************************************************************************************
+ * Pre-Processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define PIC32MX_OC_CON_OFFSET 0x0000 /* Output compare control register */
+#define PIC32MX_OC_CONCLR_OFFSET 0x0004 /* Output compare control clear register */
+#define PIC32MX_OC_CONSET_OFFSET 0x0008 /* Output compare control set register */
+#define PIC32MX_OC_CONINV_OFFSET 0x000c /* Output compare control invert register */
+#define PIC32MX_OC_R_OFFSET 0x0010 /* Output compare data register */
+#define PIC32MX_OC_RCLR_OFFSET 0x0014 /* Output compare data clear register */
+#define PIC32MX_OC_RSET_OFFSET 0x0018 /* Output compare data set register */
+#define PIC32MX_OC_RINV_OFFSET 0x001c /* Output compare data invert register */
+#define PIC32MX_OC_RS_OFFSET 0x0020 /* Output compare secondary data register */
+#define PIC32MX_OC_RSCLR_OFFSET 0x0024 /* Output compare secondary data clear register */
+#define PIC32MX_OC_RSSET_OFFSET 0x0028 /* Output compare secondary data set register */
+#define PIC32MX_OC_RSINV_OFFSET 0x002c /* Output compare secondary data invert register */
+
+/* See also TIMER2 and TIMER3 registers */
+
+/* Register Addresses ***************************************************************/
+
+#define PIC32MX_OC_CON(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CON_OFFSET)
+#define PIC32MX_OC_CONCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONCLR_OFFSET)
+#define PIC32MX_OC_CONSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONSET_OFFSET)
+#define PIC32MX_OC_CONINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONINV_OFFSET)
+#define PIC32MX_OC_R(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_R_OFFSET)
+#define PIC32MX_OC_RCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RCLR_OFFSET)
+#define PIC32MX_OC_RSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSET_OFFSET)
+#define PIC32MX_OC_RINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RINV_OFFSET)
+#define PIC32MX_OC_RS(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RS_OFFSET)
+#define PIC32MX_OC_RSCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSCLR_OFFSET)
+#define PIC32MX_OC_RSSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSSET_OFFSET)
+#define PIC32MX_OC_RSINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSINV_OFFSET)
+
+#define PIC32MX_OC1_CON (PIC32MX_OC1_K1BASE+PIC32MX_OC_CON_OFFSET)
+#define PIC32MX_OC1_CONCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
+#define PIC32MX_OC1_CONSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONSET_OFFSET)
+#define PIC32MX_OC1_CONINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONINV_OFFSET)
+#define PIC32MX_OC1_R (PIC32MX_OC1_K1BASE+PIC32MX_OC_R_OFFSET)
+#define PIC32MX_OC1_RCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_RCLR_OFFSET)
+#define PIC32MX_OC1_RSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSET_OFFSET)
+#define PIC32MX_OC1_RINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_RINV_OFFSET)
+#define PIC32MX_OC1_RS (PIC32MX_OC1_K1BASE+PIC32MX_OC_RS_OFFSET)
+#define PIC32MX_OC1_RSCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
+#define PIC32MX_OC1_RSSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSSET_OFFSET)
+#define PIC32MX_OC1_RSINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSINV_OFFSET)
+
+#if CHIP_NOC > 1
+# define PIC32MX_OC2_CON (PIC32MX_OC2_K1BASE+PIC32MX_OC_CON_OFFSET)
+# define PIC32MX_OC2_CONCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
+# define PIC32MX_OC2_CONSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONSET_OFFSET)
+# define PIC32MX_OC2_CONINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONINV_OFFSET)
+# define PIC32MX_OC2_R (PIC32MX_OC2_K1BASE+PIC32MX_OC_R_OFFSET)
+# define PIC32MX_OC2_RCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_RCLR_OFFSET)
+# define PIC32MX_OC2_RSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSET_OFFSET)
+# define PIC32MX_OC2_RINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_RINV_OFFSET)
+# define PIC32MX_OC2_RS (PIC32MX_OC2_K1BASE+PIC32MX_OC_RS_OFFSET)
+# define PIC32MX_OC2_RSCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
+# define PIC32MX_OC2_RSSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSSET_OFFSET)
+# define PIC32MX_OC2_RSINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSINV_OFFSET)
+#endif
+
+#if CHIP_NOC > 2
+# define PIC32MX_OC3_CON (PIC32MX_OC3_K1BASE+PIC32MX_OC_CON_OFFSET)
+# define PIC32MX_OC3_CONCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
+# define PIC32MX_OC3_CONSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONSET_OFFSET)
+# define PIC32MX_OC3_CONINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONINV_OFFSET)
+# define PIC32MX_OC3_R (PIC32MX_OC3_K1BASE+PIC32MX_OC_R_OFFSET)
+# define PIC32MX_OC3_RCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_RCLR_OFFSET)
+# define PIC32MX_OC3_RSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSET_OFFSET)
+# define PIC32MX_OC3_RINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_RINV_OFFSET)
+# define PIC32MX_OC3_RS (PIC32MX_OC3_K1BASE+PIC32MX_OC_RS_OFFSET)
+# define PIC32MX_OC3_RSCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
+# define PIC32MX_OC3_RSSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSSET_OFFSET)
+# define PIC32MX_OC3_RSINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSINV_OFFSET)
+#endif
+
+#if CHIP_NOC > 3
+# define PIC32MX_OC4_CON (PIC32MX_OC4_K1BASE+PIC32MX_OC_CON_OFFSET)
+# define PIC32MX_OC4_CONCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
+# define PIC32MX_OC4_CONSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONSET_OFFSET)
+# define PIC32MX_OC4_CONINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONINV_OFFSET)
+# define PIC32MX_OC4_R (PIC32MX_OC4_K1BASE+PIC32MX_OC_R_OFFSET)
+# define PIC32MX_OC4_RCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_RCLR_OFFSET)
+# define PIC32MX_OC4_RSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSET_OFFSET)
+# define PIC32MX_OC4_RINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_RINV_OFFSET)
+# define PIC32MX_OC4_RS (PIC32MX_OC4_K1BASE+PIC32MX_OC_RS_OFFSET)
+# define PIC32MX_OC4_RSCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
+# define PIC32MX_OC4_RSSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSSET_OFFSET)
+# define PIC32MX_OC4_RSINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSINV_OFFSET)
+#endif
+
+#if CHIP_NOC > 4
+# define PIC32MX_OC5_CON (PIC32MX_OC5_K1BASE+PIC32MX_OC_CON_OFFSET)
+# define PIC32MX_OC5_CONCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
+# define PIC32MX_OC5_CONSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONSET_OFFSET)
+# define PIC32MX_OC5_CONINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONINV_OFFSET)
+# define PIC32MX_OC5_R (PIC32MX_OC5_K1BASE+PIC32MX_OC_R_OFFSET)
+# define PIC32MX_OC5_RCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_RCLR_OFFSET)
+# define PIC32MX_OC5_RSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSET_OFFSET)
+# define PIC32MX_OC5_RINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_RINV_OFFSET)
+# define PIC32MX_OC5_RS (PIC32MX_OC5_K1BASE+PIC32MX_OC_RS_OFFSET)
+# define PIC32MX_OC5_RSCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
+# define PIC32MX_OC5_RSSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSSET_OFFSET)
+# define PIC32MX_OC5_RSINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSINV_OFFSET)
+#endif
+
+/* Register Bit-Field Definitions ***************************************************/
+
+/* Output compare control register */
+
+#define OC_CON_OCM_SHIFT (0) /* Bits 0-2: Output compare mode select */
+#define OC_CON_OCM_MASK (7 << OC_CON_OCM_SHIFT)
+# define OC_CON_OCM_DISABLE (0 << OC_CON_OCM_SHIFT) /* Output compare peripheral disabled */
+# define OC_CON_OCM_LOW2HI (1 << OC_CON_OCM_SHIFT) /* OCx low; compare forces high */
+# define OC_CON_OCM_HITOLOW (2 << OC_CON_OCM_SHIFT) /* OCx high; compare forces low */
+# define OC_CON_OCM_TOGGLE (3 << OC_CON_OCM_SHIFT) /* Compare event toggles OCx */
+# define OC_CON_OCM_LOWPULSE (4 << OC_CON_OCM_SHIFT) /* OCx low; output pulse on OCx*/
+# define OC_CON_OCM_HIPULSE (5 << OC_CON_OCM_SHIFT) /* OCx high; output pulse on OCx */
+# define OC_CON_OCM_PWM (6 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault disabled */
+# define OC_CON_OCM_PWMFAULT (7 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault enabled */
+#define OC_CON_OCTSEL (1 << 3) /* Bit 3: Output compare timer select */
+#define OC_CON_OCFLT (1 << 4) /* Bit 4: PWM fault condition status */
+#define OC_CON_OC32 (1 << 5) /* Bit 5: 32-bit compare more */
+#define OC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
+#define OC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
+#define OC_CON_ON (1 << 15) /* Bit 15: Output compare periperal on */
+
+/* Output compare data register -- 32-bit data register */
+
+/* Output compare secondary data register -- 32-bit data register */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CHIP_NOC > 0 */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H */
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