Rename all lpc313x to lpc31xx

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3644 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 29 insertions, 29 deletions

diff --git a/nuttx/configs/ea3131/include/board_memorymap.h b/nuttx/configs/ea3131/include/board_memorymap.h
index 576228aad..2604865c1 100755
--- a/nuttx/configs/ea3131/include/board_memorymap.h
+++ b/nuttx/configs/ea3131/include/board_memorymap.h
@@ -2,7 +2,7 @@
  * configs/ea3131/include/board_memorymap.h
  * include/arch/board/board_memorymap.h
  *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -38,7 +38,7 @@
 #define __ARCH_BOARD_BOARD_MEMORYMAP_H
 
 /* This file should never be included directly, but only indirectly via
- * lpc313x_memorymap.h.
+ * lpc31_memorymap.h.
  */
 
 /************************************************************************************
@@ -51,44 +51,44 @@
  * Definitions
  ************************************************************************************/
 
-/* If the LPC313x ROM page table is selected, then the board-logic is required
+/* If the LPC31xx ROM page table is selected, then the board-logic is required
  * to provide:
  *
  *   PGTABLE_BASE_PADDR - The physical address of the page table in ROM,
  *   PGTABLE_BASE_VADDR - The mapped address of the page table in ROM, and
- *   Mappings for each of the PSECTIONS in lpc313x_memorymap.h
+ *   Mappings for each of the PSECTIONS in lpc31_memorymap.h
  */
  
 #ifdef CONFIG_ARCH_ROMPGTABLE
-   /* The LPC313x ROM page table uses a 1-1 physical to virtual memory mapping */
+   /* The LPC31xx ROM page table uses a 1-1 physical to virtual memory mapping */
 
-#  define LPC313X_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
-#  define LPC313X_INTSRAM_VSECTION     0x11028000 /*                        Internal SRAM 96Kb-192Kb */
-#    define LPC313X_INTSRAM0_VADDR     0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
-#    define LPC313X_INTSRAM1_VADDR     0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
-#  define LPC313X_INTSROM0_VSECTION    0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
-#  define LPC313X_APB01_VSECTION       0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb  APB1 16Kb*/
-#    define LPC313X_APB0_VADDR         0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
-#    define LPC313X_APB1_VADDR         0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
-#  define LPC313X_APB2_VSECTION        0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
-#  define LPC313X_APB3_VSECTION        0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
-#  define LPC313X_APB4MPMC_VSECTION    0x17000000 /*                        8Kb */
-#    define LPC313X_APB4_VADDR         0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
-#    define LPC313X_MPMC_VADDR         0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
-#  define LPC313X_MCI_VSECTION         0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
-#  define LPC313X_USBOTG_VSECTION      0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
-#  define LPC313X_EXTSRAM_VSECTION     0x20020000 /*                        64-128Kb */
-#    define LPC313X_EXTSRAM0_VADDR     0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
-#    define LPC313X_EXTSRAM1_VADDR     0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
-#  define LPC313X_EXTSDRAM0_VSECTION   0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
-#  define LPC313X_INTC_VSECTION        0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
-#  define LPC313X_NAND_VSECTION        0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
+#  define LPC31_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
+#  define LPC31_INTSRAM_VSECTION     0x11028000 /*                        Internal SRAM 96Kb-192Kb */
+#    define LPC31_INTSRAM0_VADDR     0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
+#    define LPC31_INTSRAM1_VADDR     0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
+#  define LPC31_INTSROM0_VSECTION    0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
+#  define LPC31_APB01_VSECTION       0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb  APB1 16Kb*/
+#    define LPC31_APB0_VADDR         0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
+#    define LPC31_APB1_VADDR         0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
+#  define LPC31_APB2_VSECTION        0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
+#  define LPC31_APB3_VSECTION        0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
+#  define LPC31_APB4MPMC_VSECTION    0x17000000 /*                        8Kb */
+#    define LPC31_APB4_VADDR         0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
+#    define LPC31_MPMC_VADDR         0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
+#  define LPC31_MCI_VSECTION         0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
+#  define LPC31_USBOTG_VSECTION      0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
+#  define LPC31_EXTSRAM_VSECTION     0x20020000 /*                        64-128Kb */
+#    define LPC31_EXTSRAM0_VADDR     0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
+#    define LPC31_EXTSRAM1_VADDR     0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
+#  define LPC31_EXTSDRAM0_VSECTION   0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
+#  define LPC31_INTC_VSECTION        0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
+#  define LPC31_NAND_VSECTION        0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
 
    /* Define the address of the page table within the ROM */
 
-#  define ROMPGTABLE_OFFSET            0x0001c000  /* Offset of the ROM page table in ROM */
-#  define PGTABLE_BASE_PADDR           (LPC313X_INTSROM0_PSECTION+ROMPGTABLE_OFFSET)
-#  define PGTABLE_BASE_VADDR           (LPC313X_INTSROM0_VSECTION+ROMPGTABLE_OFFSET)
+#  define ROMPGTABLE_OFFSET          0x0001c000  /* Offset of the ROM page table in ROM */
+#  define PGTABLE_BASE_PADDR         (LPC31_INTSROM0_PSECTION+ROMPGTABLE_OFFSET)
+#  define PGTABLE_BASE_VADDR         (LPC31_INTSROM0_VSECTION+ROMPGTABLE_OFFSET)
 #endif
 
 /************************************************************************************