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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2009-12-30 17:50:26 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2009-12-30 17:50:26 +0000
commiteec25d29ad35d963df61f88c95495bab453282b0 (patch)
tree0fa8dd6558c7901059a44dd4142edfe2bbe4476d /nuttx/configs/ea3131/src/up_clkinit.c
parentea7ba8d9a64cabb45a18375b1ded3b2df1361a7b (diff)
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Completes clock initialization
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2465 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/ea3131/src/up_clkinit.c')
-rwxr-xr-xnuttx/configs/ea3131/src/up_clkinit.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/nuttx/configs/ea3131/src/up_clkinit.c b/nuttx/configs/ea3131/src/up_clkinit.c
index 7acc4c319..7a1495b15 100755
--- a/nuttx/configs/ea3131/src/up_clkinit.c
+++ b/nuttx/configs/ea3131/src/up_clkinit.c
@@ -234,13 +234,16 @@
* Public Data
****************************************************************************/
-/* Default clock configuration for the EA3131 board
+/* Default clock configuration for the EA3131 board. Every board must
+ * provide an implementation of g_boardclks. This rather complex structure
+ * is used by the boot-up logic to configure initial lpc313x clocking.
*
- * FFAST: 12MHz
- * MASTER PLL Freq: 180MHz;
- * AUDIOPLL Freq: 1024Fs, Fs = 44.1kHz
+ * FFAST: 12MHz
+ * MASTER PLL Freq: 180MHz;
+ * AUDIOPLL Freq: 1024Fs, Fs = 44.1kHz
*
* Domain Input Subdomain Divider Ratio
+ * ------------------------ ----------------- ----------------- -------------
* 0 - DOMAIN_SYS MASTER PLL(HPLL1) DOMAIN0_DIV0 1/2
* DOMAIN0_DIV1 1
* DOMAIN0_DIV2 1/2
@@ -281,7 +284,7 @@
* 11 - DOMAIN_SYSCLKO FFAST - -
*/
-const struct lpc313x_clkinit_s g_cgu_default_clks =
+const struct lpc313x_clkinit_s g_boardclks =
{
/* Domain 0 (DOMAINID_SYS), Clocks 0 - 29, Fraction dividers 0-6 */