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author | Gregory Nutt <gnutt@nuttx.org> | 2013-04-24 18:29:26 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-04-24 18:29:26 -0600 |
commit | 7a45a69800188774ffa2988aab98832462fe7cdf (patch) | |
tree | dd4f4769bf13aec2f68539933ce8facd06b0bae4 /nuttx/configs/freedom-kl25z | |
parent | 2b0558a4003a031a7e6dc0c95670473e018d8b98 (diff) | |
download | px4-nuttx-7a45a69800188774ffa2988aab98832462fe7cdf.tar.gz px4-nuttx-7a45a69800188774ffa2988aab98832462fe7cdf.tar.bz2 px4-nuttx-7a45a69800188774ffa2988aab98832462fe7cdf.zip |
Fix KL25Z clock definitions in board.h
Diffstat (limited to 'nuttx/configs/freedom-kl25z')
-rw-r--r-- | nuttx/configs/freedom-kl25z/include/board.h | 48 |
1 files changed, 29 insertions, 19 deletions
diff --git a/nuttx/configs/freedom-kl25z/include/board.h b/nuttx/configs/freedom-kl25z/include/board.h index d9bbdad04..185160c0a 100644 --- a/nuttx/configs/freedom-kl25z/include/board.h +++ b/nuttx/configs/freedom-kl25z/include/board.h @@ -57,32 +57,42 @@ #define BOARD_XTAL_FREQ 8000000 /* 8MHz crystal frequency (REFCLK) */ #define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */ -/* PLL Configuration. NOTE: Only even frequency crystals are supported that will - * produce a 2MHz reference clock to the PLL. +/* PLL Configuration. * - * PLL Input frequency: PLLIN = REFCLK/PRDIV = 4MHz/2 = 2MHz - * PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*48 = 96MHz - * MCG Frequency: PLLOUT = 96MHz + * PLL Input frequency: PLLIN = REFCLK / PRDIV0 = 8MHz / 2 = 4MHz + * PLL Output frequency: PLLOUT = PLLIN * VDIV0 = 4Mhz * 24 = 96MHz + * MCGPLLCLK Frequency: MCGPLLCLK = 96MHz */ -#define BOARD_PRDIV 2 /* PLL External Reference Divider */ -#define BOARD_VDIV 48 /* PLL VCO Divider (frequency multiplier) */ +#define BOARD_PRDIV0 2 /* PLL External Reference Divider */ +#define BOARD_VDIV0 24 /* PLL VCO Divider (frequency multiplier) */ -#define BOARD_PLLIN_FREQ (BOARD_XTAL_FREQ / BOARD_PRDIV) -#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV) -#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ +#define BOARD_PLLIN_FREQ (BOARD_XTAL_FREQ / BOARD_PRDIV0) +#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV0) +#define BOARD_MCGPLLCLK_FREQ BOARD_PLLOUT_FREQ -/* SIM CLKDIV1 dividers */ +/* MCGOUTCLK: MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or MCG's external + * reference clock that sources the core, system, bus, and flash clock. + * + * MCGOUTCLK = MCGPLLCLK = 96MHz + */ + +#define BOARD_MCGOUTCLK_FREQ BOARD_MCGPLLCLK_FREQ + +/* SIM CLKDIV1 dividers. + * + * Core/system clock + * MCGOUTCLK divided by OUTDIV1, clocks the ARM Cortex-M0+ core + * + * Bus clock + * System clock divided by OUTDIV4, clocks the bus slaves and peripherals. + */ -#define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */ -#define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */ -#define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */ -#define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */ +#define BOARD_OUTDIV1 2 /* Core/system = MCGOUTCLK / 2, 48MHz */ +#define BOARD_OUTDIV4 2 /* Bus clock = System clock / 2, 24MHz */ -#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) -#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) -#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) -#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) +#define BOARD_CORECLK_FREQ (BOARD_MCGOUTCLK_FREQ / BOARD_OUTDIV1) +#define BOARD_BUSCLK_FREQ (BOARD_CORECLK_FREQ / BOARD_OUTDIV4) /* SDHC clocking ********************************************************************/ |