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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-12-01 01:57:28 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-12-01 01:57:28 +0000 |
| commit | 9e05602549607c9b77c1e326b344b0cb77f48ece (patch) | |
| tree | 8122b7e40d5281aaa79e29def62ff6408a48ea9b /nuttx/configs/nucleus2g | |
| parent | 917a039e8412c9714ee5cee2f95b7814dbfc60a1 (diff) | |
| download | px4-nuttx-9e05602549607c9b77c1e326b344b0cb77f48ece.tar.gz px4-nuttx-9e05602549607c9b77c1e326b344b0cb77f48ece.tar.bz2 px4-nuttx-9e05602549607c9b77c1e326b344b0cb77f48ece.zip | |
typos
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3154 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/nucleus2g')
| -rwxr-xr-x | nuttx/configs/nucleus2g/include/board.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/nuttx/configs/nucleus2g/include/board.h b/nuttx/configs/nucleus2g/include/board.h index 415bf1741..138f38e68 100755 --- a/nuttx/configs/nucleus2g/include/board.h +++ b/nuttx/configs/nucleus2g/include/board.h @@ -64,10 +64,10 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC17_CCLK 80000000 /* 80Mhz*/ +#define LPC17_CCLK 80000000 /* 80Mhz */ /* Select the main oscillator as the frequency source. SYSCLK is then the frequency - * of the main osciallator. + * of the main oscillator. */ #undef CONFIG_LPC17_MAINOSC @@ -86,6 +86,8 @@ * Source clock: Main oscillator * PLL0 Multiplier value (M): 20 * PLL0 Pre-divider value (N): 1 + * + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz */ #undef CONFIG_LPC17_PLL0 @@ -107,8 +109,8 @@ (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) -/* USB divider. This divder is used when PLL1 is not enabled to get the USB clock - * from PLL0: +/* USB divider. This divider is used when PLL1 is not enabled to get the + * USB clock from PLL0: * * USBCLK = PLL0CLK / 10 = 48MHz */ |