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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2012-09-22 19:19:56 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2012-09-22 19:19:56 +0000
commit8f88f77957feaf87be4b7571a420a13682a357b9 (patch)
treee81f0bfd6ab73966a0908fe374c3eddb2505ff13 /nuttx/configs/olimex-stm32-p107
parentd49fa0f03c72b2fcc29f22ad037bc5c5a8a8d7c9 (diff)
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STM32 Ethernet, Slightly differ register layout for DM9161AEP PHY
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5177 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/olimex-stm32-p107')
-rw-r--r--nuttx/configs/olimex-stm32-p107/include/board.h12
1 files changed, 7 insertions, 5 deletions
diff --git a/nuttx/configs/olimex-stm32-p107/include/board.h b/nuttx/configs/olimex-stm32-p107/include/board.h
index d531eb112..42dd4f4d5 100644
--- a/nuttx/configs/olimex-stm32-p107/include/board.h
+++ b/nuttx/configs/olimex-stm32-p107/include/board.h
@@ -50,8 +50,6 @@
* Pre-processor Definitions
************************************************************************************/
-#define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK
-
/* Clocking *************************************************************************/
/* On-board crystal frequency is 25MHz (HSE) */
@@ -97,10 +95,14 @@
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
-/* MCO output */
-
+/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
+ *
+ * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz
+ */
+
#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
-# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10
+# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */
+# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */
#endif
/************************************************************************************